Abstract:
A method of manufacturing a white light emitting device includes dividing a phosphor sheet into phosphor film units to be applied to individual light emitting diode (LED) devices, measuring light conversion characteristics of the respective phosphor film units, classifying the phosphor film units of the phosphor sheet into a plurality of groups according to measurement results of the light conversion characteristics and combining the phosphor film units classified into the plurality of groups and an LED device having predetermined light characteristics so as to obtain target color characteristics.
Abstract:
A method of manufacturing a white light emitting device includes dividing a phosphor sheet into phosphor film units to be applied to individual light emitting diode (LED) devices, measuring light conversion characteristics of the respective phosphor film units, classifying the phosphor film units of the phosphor sheet into a plurality of groups according to measurement results of the light conversion characteristics and combining the phosphor film units classified into the plurality of groups and an LED device having predetermined light characteristics so as to obtain target color characteristics.
Abstract:
A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.
Abstract:
Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer. The first insulating film and the second insulating film may be sequentially stacked on the substrate in a vertical direction, and a longest vertical distance between an upper surface of the lower metal layer and the substrate may be less than a longest vertical distance between the upper surface of the second insulating film and the substrate.
Abstract:
A method of manufacturing a white light emitting device includes dividing a phosphor sheet into phosphor film units to be applied to individual light emitting diode (LED) devices, measuring light conversion characteristics of the respective phosphor film units, classifying the phosphor film units of the phosphor sheet into a plurality of groups according to measurement results of the light conversion characteristics and combining the phosphor film units classified into the plurality of groups and an LED device having predetermined light characteristics so as to obtain target color characteristics.
Abstract:
A semiconductor device includes a via pattern in a first interlayer insulating film, and a wiring pattern that extends in a first direction and is on the first interlayer insulating film and the via pattern. The wiring pattern includes a lower wiring line and an upper wiring line on the lower wiring line, where the lower wiring line and the upper wiring line are stacked in a second direction, where the lower wiring line is between the via pattern and the upper wiring line and is on an upper surface of the via pattern, where a first portion of the lower wiring line is on the upper surface of the via pattern and has a first thickness, and where a second portion of the lower wiring line is on an upper surface of the first interlayer insulating film and has a second thickness.
Abstract:
Integrated circuit devices including a via and methods of forming the same are provided. The methods may include forming a conductive wire structure on a substrate. The conductive wire structure may include a first insulating layer and a conductive wire stack in the first insulating layer, and the conductive wire stack may include a conductive wire and a mask layer stacked on the substrate. The method may also include forming a recess in the first insulating layer by removing the mask layer, the recess exposing the conductive wire, forming an etch stop layer and then a second insulating layer on the first insulating layer and in the recess of the first insulating layer, and forming a conductive via extending through the second insulating layer and the etch stop layer and contacting the conductive wire.
Abstract:
A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.
Abstract:
A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.
Abstract:
A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.