公开(公告)号：US12211846B2

公开(公告)日：2025-01-28

申请号：US18415863

申请日：2024-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo Kim ,  Gi Gwan Park ,  Jung Hun Choi ,  Koung Min Ryu ,  Sun Jung Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L27/092 ,  H01L29/423 ,  H01L29/739

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

公开(公告)号：US10929009B2

公开(公告)日：2021-02-23

申请号：US15966990

申请日：2018-04-30

Applicant: Samsung Electronics Co., Ltd

Inventor： Young Seok Lim ,  Hong Seok Kwon ,  Ho Min Moon ,  Mi Jung Park ,  Woo Young Park ,  Ki Hyoung Son ,  Won Ick Ahn ,  Pil Seung Yang ,  Jae Seok Yoon ,  Gi Soo Lee ,  Sun Jung Lee ,  Jae Hyeok Lee ,  Hyun Yeul Lee ,  Hyeon Cheon Jo ,  Doo Soon Choi ,  Kyung Wha Hong ,  Da Som Lee ,  Yong Joon Jeon

IPC: G06F17/00 ,  G06F3/0488 ,  G06F3/01 ,  G06F3/0482 ,  G06F3/16

Abstract: An electronic device is provided. The electronic device includes a housing, a touch screen display that includes a first edge and a second edge, a microphone, at least one speaker, a wireless communication circuit, a memory, and a processor operably connected with the touch screen display, the microphone, the at least one speaker, the wireless communication circuit, and the memory. The processor is configured to output a home screen including a plurality of application icons in a matrix pattern. The processor is configured receive an input from the first edge to the second edge. The processor is configured output a user interface on the touch screen display that includes a button that allows user to call a first operation and a plurality of cards. To call the first operation the processor is configured to receive a user input, transmit data and receive a response, and perform a task.

公开(公告)号：US10937856B2

公开(公告)日：2021-03-02

申请号：US16424996

申请日：2019-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Hun Choi ,  Young Tak Kim ,  Da Il Eom ,  Sun Jung Lee

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/78

Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device including an insulation layer; a metal resistance pattern on the insulation layer; a spacer on a side wall of the metal resistance pattern; and a gate contact spaced apart from the spacer, the gate contact extending into the insulation layer, wherein the insulation layer includes a projection projecting therefrom, the projection contacting the gate contact.

公开(公告)号：US10332954B2

公开(公告)日：2019-06-25

申请号：US15444455

申请日：2017-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Hun Choi ,  Young Tak Kim ,  Da Il Eom ,  Sun Jung Lee

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/78

Abstract: A semiconductor device and a manufacturing method thereof, the semiconductor device including an insulation layer; a metal resistance pattern on the insulation layer; a spacer on a side wall of the metal resistance pattern; and a gate contact spaced apart from the spacer, the gate contact extending into the insulation layer, wherein the insulation layer includes a projection projecting therefrom, the projection contacting the gate contact.

公开(公告)号：US20240413081A1

公开(公告)日：2024-12-12

申请号：US18652067

申请日：2024-05-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Jung Lee ,  Sang Hoon Ahn ,  Dong Gon Yoo ,  Jeong Won Hwang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device includes a via pattern in a first interlayer insulating film, and a wiring pattern that extends in a first direction and is on the first interlayer insulating film and the via pattern. The wiring pattern includes a lower wiring line and an upper wiring line on the lower wiring line, where the lower wiring line and the upper wiring line are stacked in a second direction, where the lower wiring line is between the via pattern and the upper wiring line and is on an upper surface of the via pattern, where a first portion of the lower wiring line is on the upper surface of the via pattern and has a first thickness, and where a second portion of the lower wiring line is on an upper surface of the first interlayer insulating film and has a second thickness.

公开(公告)号：US10763254B2

公开(公告)日：2020-09-01

申请号：US15333545

申请日：2016-10-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo Kim ,  Gi Gwan Park ,  Jung Hun Choi ,  Koung Min Ryu ,  Sun Jung Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L29/423 ,  H01L27/092 ,  H01L29/739

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

公开(公告)号：US11908858B2

公开(公告)日：2024-02-20

申请号：US16937912

申请日：2020-07-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Soo Kim ,  Gi Gwan Park ,  Jung Hun Choi ,  Koung Min Ryu ,  Sun Jung Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/528 ,  H01L29/423 ,  H01L27/092 ,  H01L29/739

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5283 ,  H01L29/42364 ,  H01L29/42372 ,  H01L27/0924 ,  H01L29/7391

Abstract: A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

公开(公告)号：US20240038841A1

公开(公告)日：2024-02-01

申请号：US18188399

申请日：2023-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gi Gwan PARK ,  Jung Gun You ,  Sun Jung Lee

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/417

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/41733

Abstract: There is provided a semiconductor device capable of capable of improving element performance and reliability. A semiconductor device includes a lower conductive pattern disposed on a substrate, an upper conductive pattern disposed on the lower conductive pattern, and a first plug pattern disposed between the lower conductive pattern and the upper conductive pattern and connected to the lower conductive pattern and the upper conductive pattern. The first plug pattern includes a first barrier pattern that defines a first plug recess and a first plug metal pattern that fills the first plug recess, and the first plug metal pattern includes a first molybdenum pattern and a first tungsten pattern disposed on the first molybdenum pattern.