公开(公告)号：US10535600B2

公开(公告)日：2020-01-14

申请号：US15987211

申请日：2018-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Seok Seo ,  Jong Min Baek ,  Su Hyun Bark ,  Sang Hoon Ahn ,  Hyeok Sang Oh ,  Eui Bok Lee

IPC: H01L23/52 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L29/41

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

公开(公告)号：US10510658B2

公开(公告)日：2019-12-17

申请号：US16039838

申请日：2018-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Deok Young Jung ,  Sang Bom Kang ,  Doo-Hwan Park ,  Jong Min Baek ,  Sang Hoon Ahn ,  Hyeok Sang Oh ,  Woo Kyung You

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer. The first insulating film and the second insulating film may be sequentially stacked on the substrate in a vertical direction, and a longest vertical distance between an upper surface of the lower metal layer and the substrate may be less than a longest vertical distance between the upper surface of the second insulating film and the substrate.

公开(公告)号：US10475739B2

公开(公告)日：2019-11-12

申请号：US15840128

申请日：2017-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Kyung You ,  Eui Bok Lee ,  Jong Min Baek ,  Su Hyun Bark ,  Jang Ho Lee ,  Sang Hoon Ahn ,  Hyeok Sang Oh

IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate comprising a lower wire, an etch stop layer on the substrate, an interlayer insulating layer on the etch stop layer, an upper wire disposed in the interlayer insulating layer and separated from the lower wire and a via formed in the interlayer insulating layer and the etch stop layer and connecting the lower wire with the upper wire, wherein the via comprises a first portion in the etch stop layer and a second portion in the interlayer insulating layer, and wherein a sidewall of the first portion of the via increases stepwise.

公开(公告)号：US10461027B2

公开(公告)日：2019-10-29

申请号：US16008319

申请日：2018-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok Lee ,  Jong Min Baek ,  Sang Hoon Ahn ,  Hyeok Sang Oh

IPC: H01L23/58 ,  H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

Abstract: A semiconductor device includes a lower insulating layer disposed on a substrate. A conductive pattern is formed in the lower insulating layer. A middle insulating layer is disposed on the lower insulating layer and the conductive pattern. A via control region is formed in the middle insulating layer. An upper insulating layer is disposed on the middle insulating layer and the via control region. A via plug is formed to pass through the via control region and to be connected to the conductive pattern. The via control region has a lower etch rate than the middle insulating layer.