公开(公告)号：US09984921B2

公开(公告)日：2018-05-29

申请号：US15802724

申请日：2017-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon Ahn ,  Jong Min Baek ,  Myung Geun Song ,  Woo Kyung You ,  Byung Kwon Cho ,  Byung Hee Kim ,  Na Ein Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.

公开(公告)号：US09812353B2

公开(公告)日：2017-11-07

申请号：US15353984

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang Hoon Ahn ,  Jong Min Baek ,  Myung Geun Song ,  Woo Kyung You ,  Byung Kwon Cho ,  Byung Hee Kim ,  Na Ein Lee

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32053 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76883 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295

Abstract: A method of manufacturing a semiconductor device includes forming grooves in a first dielectric layer on a substrate, the first dielectric layer including a first part between the grooves, forming a first barrier layer and an interconnect layer in each groove, recessing the interconnect layer and the first barrier layer, forming a capping pattern on the recessed interconnect layer, etching at least a portion of the first part by a first etching process, sequentially etching the capping pattern and the at least a portion of the IMD part by a second etching process to form a trench, conformally forming a second barrier layer in the trench and on the recessed interconnection layer, and forming a second dielectric layer on the second barrier layer not to fill the trench such that an air gap is formed in the trench.