Vertical memory device
    1.
    发明授权

    公开(公告)号:US10685973B2

    公开(公告)日:2020-06-16

    申请号:US15942683

    申请日:2018-04-02

    Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

    Fingerprint recognition device and smart card

    公开(公告)号:US12249175B2

    公开(公告)日:2025-03-11

    申请号:US17569059

    申请日:2022-01-05

    Abstract: A fingerprint recognition device is provided. The fingerprint recognition device includes an image acquisition module acquiring a fingerprint image including an input fingerprint, a preprocessing module generating a preprocessed image by preprocessing the fingerprint image, a minutiae extraction module extracting coordinates of each of minutiae and orientation points of the input fingerprint from the preprocessed image and a fake detection module receiving regions-of-interest (ROIs), including the coordinates of each of the minutiae or orientation points of the input fingerprint, and determining whether the input fingerprint is a fake by performing learning using the received ROIs.

    Vertical memory device
    5.
    发明授权

    公开(公告)号:US11233067B2

    公开(公告)日:2022-01-25

    申请号:US16898720

    申请日:2020-06-11

    Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

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