公开(公告)号：US10685973B2

公开(公告)日：2020-06-16

申请号：US15942683

申请日：2018-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Kyu Song ,  Ki Yoon Kang ,  Jae Hoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11551 ,  H01L23/00

Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

公开(公告)号：US10522562B2

公开(公告)日：2019-12-31

申请号：US16149249

申请日：2018-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C16/04

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

公开(公告)号：US11004865B2

公开(公告)日：2021-05-11

申请号：US16692385

申请日：2019-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

IPC: H01L27/11582 ,  H01L27/11556 ,  G11C16/04

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

公开(公告)号：US11233067B2

公开(公告)日：2022-01-25

申请号：US16898720

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Kyu Song ,  Ki Yoon Kang ,  Jae Hoon Jang

IPC: H01L27/11582 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11551

Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

公开(公告)号：US20200091189A1

公开(公告)日：2020-03-19

申请号：US16692385

申请日：2019-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Kim ,  Shin Hwan Kang ,  Jae Hoon Jang ,  Kohji Kanamori

IPC: H01L27/11582

Abstract: A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.

公开(公告)号：US20190067321A1

公开(公告)日：2019-02-28

申请号：US15942683

申请日：2018-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Kyu SONG ,  Ki Yoon Kang ,  Jae Hoon Jang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/00

Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

公开(公告)号：US09853049B2

公开(公告)日：2017-12-26

申请号：US15241450

申请日：2016-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Kim ,  Jae Hoon Jang ,  Byoung Keun Son

IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/528 ,  H01L23/532 ,  H01L29/08 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11582 ,  H01L27/0688 ,  H01L27/11568 ,  H01L27/11573

Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel areas passing through the gate structure and extending in a direction perpendicular to the upper surface of the substrate, a source area disposed on the substrate to extend in a first direction and including impurities, and a common source line extending in the direction perpendicular to the upper surface of the substrate to be connected to the source area, and including a plurality of layers containing different materials.

公开(公告)号：US10103165B2

公开(公告)日：2018-10-16

申请号：US15481609

申请日：2017-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Hwan Son ,  Won Chul Jang ,  Dong Seog Eun ,  Jae Hoon Jang

IPC: H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11565

Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.