公开(公告)号：US20190067321A1

公开(公告)日：2019-02-28

申请号：US15942683

申请日：2018-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Kyu SONG ,  Ki Yoon Kang ,  Jae Hoon Jang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L23/00

Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

公开(公告)号：US10685973B2

公开(公告)日：2020-06-16

申请号：US15942683

申请日：2018-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Kyu Song ,  Ki Yoon Kang ,  Jae Hoon Jang

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11551 ,  H01L23/00

Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.

公开(公告)号：US11233067B2

公开(公告)日：2022-01-25

申请号：US16898720

申请日：2020-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Moon Kyu Song ,  Ki Yoon Kang ,  Jae Hoon Jang

IPC: H01L27/11582 ,  H01L23/00 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11551

Abstract: A vertical memory device includes a substrate including a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, a channel structure on the cell array region and extending in a direction perpendicular to an upper surface of the substrate while penetrating through the plurality of gate electrode layers, a dummy channel structure on the connection region and extending in the direction perpendicular to the upper surface of the substrate while penetrating through at least a portion of the plurality of gate electrode layers, and a support insulating layer between a portion of the plurality of gate electrode layers and the dummy channel structure. The plurality of gate electrode form a stepped structure on the connection region.