公开(公告)号：US20220223592A1

公开(公告)日：2022-07-14

申请号：US17705565

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seonghwa PARK ,  Hongbae PARK ,  Jaehyun LEE ,  Jonghan LEE ,  Dabok JEONG ,  Minseok JO

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/308

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern and the second gate pattern being spaced apart from each other, and a separation pattern that separates the first gate pattern and the second gate pattern from each other. The first gate pattern includes a first high-k dielectric pattern and a first metal-containing pattern on the first high-k dielectric pattern, the first metal-containing pattern covering a sidewall of the first high-k dielectric pattern. The second gate pattern includes a second high-k dielectric pattern and a second metal-containing pattern on the second high-k dielectric pattern, and the separation pattern is in direct contact with the first metal-containing pattern and spaced apart from the first high-k dielectric pattern.

公开(公告)号：US20250126871A1

公开(公告)日：2025-04-17

申请号：US18630286

申请日：2024-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon PARK ,  Minseok JO ,  Jinyoung CHOI ,  Jun-Youp LEE ,  Hakjong LEE

IPC: H01L29/423 ,  H01L21/762 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device may include an active pattern on a substrate, defined by a trench, and extending in a first direction, a device isolation layer filling the trench, the substrate including a first surface in contact with a bottom surface of the device isolation layer and a second surface opposite to the first surface, a gate electrode extending in a second direction and cross the active pattern, the second direction crossing the first direction, a first division structure spaced apart from the gate electrode in the first and extending in the second direction, and a power delivery network layer on the second surface of the substrate. The first division structure may penetrate the device isolation layer, and a bottom surface of the first division structure may be coplanar with the second surface of the substrate.

公开(公告)号：US20230187519A1

公开(公告)日：2023-06-15

申请号：US17896523

申请日：2022-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyung SON ,  Seungje KIM ,  Jiwon PARK ,  Jaepo LIM ,  Minseok JO ,  Seunghyun LIM ,  Jinyoung CHOI

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/786 ,  H01L29/775 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/78696 ,  H01L29/775 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66439

Abstract: A semiconductor device is provided. The semiconductor device includes: a substrate with an active region extending in a first direction; an element isolation layer, adjacent to the active region, in the substrate; a gate electrode on the substrate and extending in a second direction which crosses the first direction; a plurality of channel layers on the active region, spaced apart from each other along a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate electrode; and a source/drain region provided in a recess of the active region adjacent to the gate electrode, and connected to the plurality of channel layers. In the first direction, the gate electrode has a first length on the active region and a second length, greater than the first length, on the element isolation layer.

公开(公告)号：US20240304623A1

公开(公告)日：2024-09-12

申请号：US18472777

申请日：2023-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hanyoung SONG ,  Jiwon PARK ,  Minseok JO

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a first fin-type active region and a second fin-type active region extending in a first lateral direction on a substrate, a first gate line extending in a second lateral direction intersecting the first lateral direction on the first fin-type active region, a second gate line apart from the first gate line in the second lateral direction on the second fin-type active region and extending along an extension line of the first gate line in the second lateral direction, and a gate cut insulating pattern between the first gate line and the second gate line, wherein, for at least one of the first gate line and the second gate line, a width of a terminal gate portion, which is adjacent to the gate cut insulating pattern, in the first lateral direction is less than a width of another portion in the first lateral direction.