公开(公告)号：US20170162674A1

公开(公告)日：2017-06-08

申请号：US15355781

申请日：2016-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin Bum KIM ,  Kang Hun MOON ,  Choeun LEE ,  Kyung Yub JEON ,  Sujin JUNG ,  Haegeon JUNG ,  Yang XU

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.

公开(公告)号：US20190109214A1

公开(公告)日：2019-04-11

申请号：US16197752

申请日：2018-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub JEON ,  Tae Yong KWON ,  Oh Seong KWON ,  Soo Yeon JEONG ,  Yong Hee PARK ,  Jong Ryeol YOO

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78 ,  H01L29/423

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.

公开(公告)号：US20190198340A1

公开(公告)日：2019-06-27

申请号：US16135669

申请日：2018-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeongseop KIM ,  Kyung Yub JEON ,  Seul Gi HAN

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/311

Abstract: A method for defining a length of a fin including forming a plurality of first slice walls on a mask material layer, which is provided over the fin, using a plurality of hard mask patterns, providing a plurality of fill mask patterns self-aligned with respect to the plurality of first slice walls to expose one or more select areas between one or more pairs of adjacent ones of the plurality of first slice walls, and providing a trim mask pattern including one or more openings and self-aligned with respect to the plurality of second slice walls to expose one or more of the plurality of first slice walls may be provided.

公开(公告)号：US20180350952A1

公开(公告)日：2018-12-06

申请号：US15878711

申请日：2018-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Yub JEON ,  Tae Yong KWON ,  Oh Seong KWON ,  Soo Yeon JEONG ,  Yong Hee PARK ,  Jong Ryeol YOO

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/66666 ,  H01L29/1037 ,  H01L29/4238 ,  H01L29/66553 ,  H01L29/7827

Abstract: A vertical tunnel field effect transistor (VTFET) including a fin structure protruding from a substrate including a source/drain region, an epitaxially-grown source/drain structure on the fin structure, a cap including pillar portions, the pillar portions covering side surfaces of the epitaxially-grown source/drain structure and partially covering side surfaces of a top portion of the fin structure, a gate insulator covering remaining portions of the side surfaces of the fin structure under the pillar portions of the cap, a work function metal gate on the gate insulator, and a separation pattern surrounding a bottom portion of a fin structure such that the work function metal gate is vertically between the cap and the separation pattern, the separation pattern electrically isolating the work function metal gate from the source/drain region, and a method of manufacturing the same may be provided.