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公开(公告)号：US11870615B2
公开(公告)日：2024-01-09
申请号：US17835373
申请日：2022-06-08
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyeongjoon Ko , Jaehyun Park , Junhan Bae , Gyeongseok Song , Jongjae Ryu
CPC classification number: H04L25/03057 , H03K3/037 , H03K19/20
Abstract: Provided are a summing circuit and an equalizer including the summing circuit. The summing circuit includes: a reference signal generator generating a first reference signal and a second reference signal, based on a coefficient code; a first non-overlap clock buffer generating a first switching signal and a second switching signal by using the first reference signal; and a first current source receiving the first switching signal and the second switching signal generated by the first non-overlap clock buffer, generating a first output current by using a bias voltage, and outputting the first output current to an output line, wherein the first switching signal includes a switching signal and a complementary switching signal that is a complementary signal to the switching signal, and wherein a logic low period of the second switching signal is included in a logic high period of the complementary switching signal of the first switching signal.
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公开(公告)号：US11700012B2
公开(公告)日：2023-07-11
申请号：US17306421
申请日：2021-05-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeongjoon Ko , Junhan Bae , Hanseok Kim , Byeonggyu Park , Jaehyun Park , Hobin Song , Sooeun Lee
Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.
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公开(公告)号：US09654118B2
公开(公告)日：2017-05-16
申请号：US15179202
申请日：2016-06-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junhan Bae , Kee-Won Kwon , Kyungho Kim , Jung Hoon Chun , Youngsoo Sohn , Seok Kim
CPC classification number: H03L7/0891 , H03D13/004 , H03L7/081 , H03L7/085 , H03L7/087 , H03L7/0995 , H03L7/104 , H03L7/107 , H03L7/1072
Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.
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公开(公告)号：US12003250B2
公开(公告)日：2024-06-04
申请号：US17837752
申请日：2022-06-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeongjoon Ko , Jaehyun Park , Junhan Bae , Gyeongseok Song , Jongjae Ryu
CPC classification number: H03M1/682 , H03M1/687 , H03M1/747 , H03M1/0617 , H03M1/66
Abstract: A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.
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公开(公告)号：US11973623B2
公开(公告)日：2024-04-30
申请号：US17834563
申请日：2022-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeongjoon Ko , Hanseok Kim , Jaehyun Park , Junhan Bae , Gyeongseok Song , Jongjae Ryu
CPC classification number: H04L25/03057 , H04B1/16 , H04L25/03878 , H04L2025/03445
Abstract: A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.
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Patent Agency Ranking
公开(公告)号：US11888656B2
公开(公告)日：2024-01-30
申请号：US17834262
申请日：2022-06-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyeongjoon Ko , Hanseok Kim , Jaehyun Park , Junhan Bae , Gyeongseok Song , Jongjae Ryu
IPC: H04L25/03
CPC classification number: H04L25/03267 , H04L25/03121 , H04L25/03146 , H04L2025/0349
Abstract: Provided is an equalizer including: an input amplifier configured to amplify and output an input signal; a first equalization circuit including a first sampling circuit, a first arithmetic circuit, and a second arithmetic circuit, the first sampling circuit being configured to generate and output 1-1 to 1-N feedback signals, wherein N is a natural number greater than or equal to 2; and a second equalization circuit including a second sampling circuit, a third arithmetic circuit, and a fourth arithmetic circuit, the second sampling circuit being configured to generate and output 2-1 to 2-M feedback signals, wherein M is a natural number greater than or equal to 2.
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公开(公告)号：US11733727B2
公开(公告)日：2023-08-22
申请号：US17680386
申请日：2022-02-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Junhan Bae , Gyeongseok Song , Kyeong-Joon Ko , Jaehyun Park , Hajung Park , Ho-Bin Song
CPC classification number: G05F3/205 , H03F3/16 , H03K17/223
Abstract: Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.
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公开(公告)号：US12217041B2
公开(公告)日：2025-02-04
申请号：US17573849
申请日：2022-01-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sangun Bang , Dongjo Kim , Jaehyun Bae , Junhan Bae , Duseung Oh , Sungeun Lee , Arom Lee
Abstract: A portable device and an operating method of the same are provided. The portable device includes a power line communication module performing power line communication with an external device, a memory module storing firmware data, and a controller controlling the power line communication module and the memory module, wherein the power line communication module sequentially provides an update initiation signal and firmware data to the external device, and provides an update end signal to the external device in response to a response signal transmitted by the external device.
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公开(公告)号：US12074469B2
公开(公告)日：2024-08-27
申请号：US17340045
申请日：2021-06-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sejong Park , Minkyu Kwon , Taejeong Kim , Junhan Bae , Suji Lee , Hyeonje Choe
IPC: H02J7/00
CPC classification number: H02J7/007182 , H02J7/00718
Abstract: An electronic device includes a charging integrated circuit (IC) including a direct charging circuit that charges a battery; and an application processor that issues a request to an external power source to output a maximum voltage corresponding to a target current, performs a ramp-up operation on a charging current input to the charging IC on the basis of the maximum voltage, compensates for a difference between the charging current and the target current in response to the charging current entering a constant current period, and enters a sleep mode during the constant current period in response to that the charging current reaching the target current.
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公开(公告)号：US20220400035A1
公开(公告)日：2022-12-15
申请号：US17834563
申请日：2022-06-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyeongjoon Ko , Hanseok Kim , Jaehyun Park , Junhan Bae , Gyeongseok Song , Jongjae Ryu
Abstract: A latch circuit and an equalizer including the same are provided. The equalizer includes: an even data path configured to receive a reception data signal and including a first summing circuit and a first latch circuit; and an odd data path configured to receive the reception data signal and including a second summing circuit and a second latch circuit. An even data signal output from the first latch circuit is configured to be input to the second summing circuit, and an odd data signal output from the second latch circuit is configured to be input to the first summing circuit. Each of the first latch circuit and the second latch circuit includes a latch and a multiplexer.
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