公开(公告)号：US20220149863A1

公开(公告)日：2022-05-12

申请号：US17306421

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeongjoon Ko ,  Junhan Bae ,  Hanseok Kim ,  Byeonggyu Park ,  Jaehyun Park ,  Hobin Song ,  Sooeun Lee

IPC: H03M1/74 ,  H04B1/16 ,  H04L25/03

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

公开(公告)号：US11700012B2

公开(公告)日：2023-07-11

申请号：US17306421

申请日：2021-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeongjoon Ko ,  Junhan Bae ,  Hanseok Kim ,  Byeonggyu Park ,  Jaehyun Park ,  Hobin Song ,  Sooeun Lee

IPC: H03M1/74 ,  H04B1/16 ,  H04L25/03 ,  H03M1/66 ,  H03M7/16

CPC classification number: H03M1/742 ,  H03M1/66 ,  H03M7/165 ,  H04B1/16

Abstract: A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

公开(公告)号：US12288578B2

公开(公告)日：2025-04-29

申请号：US17864736

申请日：2022-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghye Cho ,  Kijun Lee ,  Myungkyu Lee ,  Eunae Lee ,  Byeonggyu Park ,  Yeonggeol Song

IPC: G11C11/406 ,  G11C11/4093

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cell rows, a row hammer management circuit, and a refresh control circuit. The row hammer management circuit captures row addresses accompanied by first active commands randomly selected from active commands, each of which has a first selection probability that is uniform, from an external memory controller during a reference time interval, and selects at least one row address from among the captured row addresses as a hammer address a number of times proportional to access counts of an active command corresponding to the at least one row address during the reference time interval. The refresh control circuit receives the hammer address and performs a hammer refresh operation on one or more victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.