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公开(公告)号：US11626143B2
公开(公告)日：2023-04-11
申请号：US17481995
申请日：2021-09-22
Inventor： Hyeran Kim , Junyeol Lee , Jung-Hoon Chun
Abstract: An output driver includes a pre driver including pre driving circuits, each including first and second pre pumps, and a main driver including main driving circuits, each including first and second main pumps. Each of the first and second pre pumps includes a first driving capacitor, and each of the first and second main pumps includes a second driving capacitor. During a first half cycle of a clock signal, the first pre pump and the first main pump perform a precharge operation, and the second pre pump and the second main pump perform a first driving operation, and during a second half cycle of the clock signal, the first pre pump and the first main pump perform the first driving operation, and the second pre pump and the second main pump perform the precharge operation. Capacitances of the first and second driving capacitors are different.
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公开(公告)号：US10483985B2
公开(公告)日：2019-11-19
申请号：US15834342
申请日：2017-12-07
Inventor： Chisung Bae , Sangjoon Kim , Yoonmyung Lee , Jaehong Jung , Jung-Hoon Chun
Abstract: An oscillator using a supply regulation loop and a method of operating the oscillator are provided. The oscillator includes a reference voltage generator configured to generate reference voltages from a supply voltage, a supply regulation loop circuit including a first operational amplifier and a transistor, the first operational amplifier being configured to receive a first reference voltage of the reference voltages, and the transistor being connected to an output terminal of the first operational amplifier, and a frequency locked loop (FLL) circuit configured to generate a clock signal, based on an input voltage determined based on a current flowing in the transistor and a second reference voltage of the reference voltages, wherein the first operational amplifier may include an input terminal configured to receive the first reference voltage and to receive negative feedback from the transistor, and the output terminal being configured to generate an output voltage independent of noise of the supply voltage.
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公开(公告)号：US20190280848A1
公开(公告)日：2019-09-12
申请号：US16108310
申请日：2018-08-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Ha Kim , Hwa Seok Oh , Jin Hyeok Choi , Jung-Hoon Chun
Abstract: A semiconductor circuit including a clocked comparator and an offset application circuit. The clocked comparator is configured to receive a first input signal and a second input signal from a host and compare the first input signal and the second input signal. The offset application circuit is configured to apply an offset to the first input signal. The clocked comparator is configured to be driven based on a reference clock provided from the host.
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公开(公告)号：US12230321B2
公开(公告)日：2025-02-18
申请号：US17830004
申请日：2022-06-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jung-Hoon Chun , Jiho Song , Yoonmyung Lee , Jua Lee
Abstract: A device with a neural network includes: a synaptic memory cell comprising a resistive memory element, which is disposed along an output line and which has either one of a first resistance value and a second resistance value, and configured to generate a column signal based on the resistive memory element and an input signal in response to the input signal being received through an input line; a reference memory cell comprising a reference memory element, which is disposed along a reference line and which has the second resistance value different from the first resistance value, and configured to generate a reference signal based on the reference memory element and the input signal; and an output circuit configured to generate an output signal for the output line from the column signal and the reference signal.
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Patent Agency Ranking
公开(公告)号：US11146378B2
公开(公告)日：2021-10-12
申请号：US16889077
申请日：2020-06-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae-Jin Kim , Jung-Hoon Chun , Jae Youl Lee , Hyun Wook Lim
Abstract: A signal receiving device may not need to consider jitter characteristics of a received signal by including a transition detecting device which receives first to third input signals having different signal levels for each unit interval, compares whether a signal level of a first differential signal, which is a differential signal between the first input signal and the second input signal among the first to third input signals, is greater than a first reference signal level to output a first comparison signal, and compares whether the signal level of the first differential signal is greater than a second reference signal level different from the first reference signal level to output a second comparison signal, and a clock data recovering device which recovers a clock signal embedded in the first to third input signals on the basis of the first and second comparison signals to output the recovery clock signal.
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公开(公告)号：US10567124B2
公开(公告)日：2020-02-18
申请号：US15867034
申请日：2018-01-10
Inventor： Sung-Ha Kim , Jung-Hoon Chun
IPC: H04L1/24 , H03M9/00 , G06F11/273 , G06F11/22 , G06F11/267
Abstract: A serial communication interface circuit includes a transmitter configured to convert first parallel data into first serial data and transmit the first serial data through an output port; a receiver configured to receive second serial data through an input port and convert the second serial data into second parallel data; a test controller configured to generate at least one test control signal; and an embedded external loopback circuit configured to form an external loopback path between the output port and the input port to receive the first serial data and output the second serial data according to at least one channel model in response to the at least one test control signal in a test mode.
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公开(公告)号：US20180212610A1
公开(公告)日：2018-07-26
申请号：US15834342
申请日：2017-12-07
Inventor： Chisung Bae , Sangjoon Kim , Yoonmyung Lee , Jaehong Jung , Jung-Hoon Chun
CPC classification number: H03L3/00 , H03L1/00 , H03L5/00 , H03L7/02 , H03L7/06 , H03L7/099 , H03L7/0995
Abstract: An oscillator using a supply regulation loop and a method of operating the oscillator are provided. The oscillator includes a reference voltage generator configured to generate reference voltages from a supply voltage, a supply regulation loop circuit including a first operational amplifier and a transistor, the first operational amplifier being configured to receive a first reference voltage of the reference voltages, and the transistor being connected to an output terminal of the first operational amplifier, and a frequency locked loop (FLL) circuit configured to generate a clock signal, based on an input voltage determined based on a current flowing in the transistor and a second reference voltage of the reference voltages, wherein the first operational amplifier may include an input terminal configured to receive the first reference voltage and to receive negative feedback from the transistor, and the output terminal being configured to generate an output voltage independent of noise of the supply voltage.
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公开(公告)号：US09658643B2
公开(公告)日：2017-05-23
申请号：US14623069
申请日：2015-02-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-Kyun Jeong , Jung-Hoon Chun , June-Hee Lee , Won-Ho Choi
CPC classification number: G06F1/08 , G06F13/4068
Abstract: A data interface includes a first sampler sampling a first bitset and a second sampler sampling a second bitset. The first bitset includes a first bit which is included in a first image data and a third bit which is included in a second image, and the second bitset includes a second bit which is included in the first image data and is a higher-order bit than the first bit and a fourth bit which is included in the second image data and is a higher-order bit than the third bit. The data interface further includes a clock generator configured to adjust a sampling timing of the first and second bitsets based on a multi-phase clock, and a clock data recovery (CDR) circuit shared by the first sampler, the second sampler and configured to output the multi-phase clock to the clock generator.
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公开(公告)号：US09356772B2
公开(公告)日：2016-05-31
申请号：US14489986
申请日：2014-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Hee Lee , Jongshin Shin , YoungKyun Jeong , Dongchul Choi , Jung-Hoon Chun
CPC classification number: H04L7/033 , H03L7/07 , H03L7/0807 , H03L7/0814 , H03L7/087 , H03L7/091 , H04L27/22
Abstract: A clock data recovery circuit includes a sampler to sample incoming data bits, a phase detector to generate an edge position signal and a polarity signal based on the sampled incoming data, a finite state machine to save a current edge position state, a polarity decision unit to generate a polarity inversion signal to invert the polarity signal, a gain controller to generate a tracking bandwidth signal, a recovery loop configured to adjust an edge offset of the reference clock, and a bit selector configured to recover the incoming data. The clock data recovery circuit has a first latency at a first operation mode and a second latency at a second operation mode. The phase detector in the clock data recovery circuit may include a first phase detector and a second detector combined together for a low latency and low lock time of the clock data recovery circuit.
Abstract translation: 时钟数据恢复电路包括：采样器，用于对输入的数据位进行采样;相位检测器，用于根据采样的输入数据产生边沿位置信号和极性信号;有限状态机，用于保存当前边沿位置状态;极性判定单元 产生极性反转信号以反转极性信号，增益控制器产生跟踪带宽信号;恢复环路，被配置为调整参考时钟的边沿偏移;以及位选择器，被配置为恢复输入数据。 时钟数据恢复电路在第一操作模式下具有第一等待时间，在第二操作模式下具有第二等待时间。 时钟数据恢复电路中的相位检测器可以包括第一相位检测器和第二检测器，其组合在一起，用于时钟数据恢复电路的低等待时间和低锁定时间。
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