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公开(公告)号：US20220367416A1
公开(公告)日：2022-11-17
申请号：US17671065
申请日：2022-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongkwan Lee , Seunghwan Kim , Jungjoo Kim , Jongwan Kim , Hyunki Kim , Junwoo Park , Hyunggil Baek , Junga Lee , Taejun Jeon
IPC: H01L25/065 , H01L23/00 , H01L23/498 , H01L23/538
Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.
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公开(公告)号：US11334457B1
公开(公告)日：2022-05-17
申请号：US16839675
申请日：2020-04-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hohyun Shin , Jongwan Kim , Hyungi Kim , Hyunsung Shin , Dongmin Kim , Myeongo Kim , Kwangil Park , Youngsoo Sohn
Abstract: A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.
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公开(公告)号：US12132007B2
公开(公告)日：2024-10-29
申请号：US18103584
申请日：2023-01-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jongwan Kim , Kyong Hwan Koh , Juhyeon Oh , Yongkwan Lee
IPC: H01L23/552 , H01L21/56 , H01L23/498 , H01L23/00
CPC classification number: H01L23/552 , H01L21/568 , H01L23/49816 , H01L23/49838 , H01L24/16 , H01L2224/16227
Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.
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公开(公告)号：US20230082412A1
公开(公告)日：2023-03-16
申请号：US17747131
申请日：2022-05-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongkwan Lee , Seunghwan Kim , Jungjoo Kim , Jongwan Kim , Junwoo Park
IPC: H01L23/367 , H01L25/065 , H01L25/16 , H01L23/498 , H01L23/48
Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate, an interposer including a lower protective layer, conductive connectors connecting the package substrate to the interposer, a semiconductor chip arranged between the package substrate and the interposer, and cooling patches arranged between the semiconductor chip and the interposer and having cylindrical shapes, wherein each of the cooling patches includes the same material as each of the conductive connectors, a height of each of the cooling patches is less than or equal to a diameter of each of the cooling patches, and thermal conductivity of each of the cooling patches is greater than thermal conductivity of the lower protective layer.
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公开(公告)号：US10067584B2
公开(公告)日：2018-09-04
申请号：US14838710
申请日：2015-08-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Inkyeong Yoo , Jungwoo Kim , Byeonghak Kang , Kwonyoung Kim , Jongwan Kim
Abstract: A film for writing may include: a rough layer, including a non-flat surface, configured to transmit a first light beam and a second light beam of different wavelength bands; and/or a photonic crystal layer, arranged on the rough layer, configured to transmit the first light beam and configured to reflect the second light beam. A film for writing, which transmits visible rays, may include: a non-flat layer. A difference between a maximum thickness and a minimum thickness of the non-flat layer may be from about 220 nanometers (nm) to about 2 microns (μm). A film for writing may include: a first layer; and/or a second layer on the first layer. The first layer may be configured to transmit first and second light beams of different frequency bands. The second layer may be configured to transmit the first light beam, but to reflect the second light beam.
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Patent Agency Ranking
公开(公告)号：US20240128190A1
公开(公告)日：2024-04-18
申请号：US18486546
申请日：2023-10-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seunghwan Kim , Yongkwan Lee , Gyuhyeong Kim , Jungjoo Kim , Jongwan Kim , Junwoo Park , Taejun Jeon , Junhyeung Jo
IPC: H01L23/528 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31
CPC classification number: H01L23/5283 , H01L21/485 , H01L21/56 , H01L23/3157 , H01L24/05 , H01L24/13 , H01L2224/05008 , H01L2224/13026
Abstract: A semiconductor package includes a lower substrate including a lower interconnection layer; an upper substrate on the lower substrate, a recessed surface having a step difference, and an upper interconnection layer having a through-hole extending from the recessed surface to the first surface of the upper substrate and electrically connected to the lower interconnection layer; semiconductor chip between the recessed surface of the upper substrate and the lower substrate and including connection pads electrically connected to the lower interconnection layer; interconnect structure between the second surface of the upper substrate and the lower substrate and electrically connecting the lower interconnection layer to the upper interconnection layer; and an insulating member including a first portion covering at least a portion of the semiconductor chip and interconnect structure, a second portion extending from the first portion into the through-hole, and a third portion covering at least a portion of the first surface.
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公开(公告)号：US11581266B2
公开(公告)日：2023-02-14
申请号：US17212035
申请日：2021-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jongwan Kim , Kyong Hwan Koh , Juhyeon Oh , Yongkwan Lee
IPC: H01L23/552 , H01L23/498 , H01L21/56 , H01L23/00
Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.
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公开(公告)号：US12205925B2
公开(公告)日：2025-01-21
申请号：US17671065
申请日：2022-02-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongkwan Lee , Seunghwan Kim , Jungjoo Kim , Jongwan Kim , Hyunki Kim , Junwoo Park , Hyunggil Baek , Junga Lee , Taejun Jeon
IPC: H01L25/065 , H01L23/00 , H01L23/498 , H01L23/538
Abstract: A semiconductor package includes a package substrate having a communication hole extending from an upper surface of the package substrate to a lower surface of the package substrate, a semiconductor chip attached to the upper surface of the package substrate, an auxiliary chip attached to the lower surface of the package substrate, external connection terminals attached to the lower surface of the package substrate and spaced apart from the auxiliary chip, and an encapsulant encapsulating the semiconductor chip and the auxiliary chip and filling the communication hole.
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公开(公告)号：US12057357B2
公开(公告)日：2024-08-06
申请号：US17212417
申请日：2021-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kyong Hwan Koh , Jongwan Kim , Juhyeon Oh , Yongkwan Lee
CPC classification number: H01L23/13 , H01L21/4803 , H01L21/561 , H01L23/3107 , H01L23/49838 , H01L23/49827 , H01L24/06 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/06135 , H01L2224/48227 , H01L2224/49173 , H01L2224/73265
Abstract: A semiconductor package includes a base substrate that includes a first surface and a second surface that face each other, a plurality of first metal line patterns disposed on the first surface, a plurality of second metal line patterns disposed on the second surface, a plurality of vias that penetrate the base substrate and connect the first metal line patterns to the second metal line patterns, a semiconductor chip disposed on the first surface, and a molding member that covers the first surface and the semiconductor chip. The base substrate includes at least one recess at a corner of the base substrate. The recess extends from the first surface toward the second surface. The molding member includes a protrusion that fills the recess.
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公开(公告)号：US20230378094A1
公开(公告)日：2023-11-23
申请号：US18104650
申请日：2023-02-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Junwoo Park , Yongkwan Lee , Seunghwan Kim , Jungjoo Kim , Jongwan Kim , Taejun Jeon , Junhyeung Jo
IPC: H01L23/00 , H01L23/538 , H01L23/498 , H01L23/31 , H10B80/00
CPC classification number: H01L23/562 , H01L23/5383 , H01L23/5386 , H01L23/5385 , H01L23/49811 , H01L23/3128 , H10B80/00 , H01L2224/16227 , H01L24/16 , H01L2224/32225 , H01L24/32 , H01L2224/73204 , H01L24/73
Abstract: A semiconductor package includes a support wiring structure, a semiconductor chip on the support wiring structure, a connection structure on the support wiring structure and spaced apart from the semiconductor chip in a horizontal direction, an interposer including a central portion and an outer portion and having a recess portion provided on a lower surface of the central portion facing the semiconductor chip, wherein the central portion is on the semiconductor chip and the connection structure is connected to the outer portion, and a metal plate disposed along a portion of a surface of the recess portion inside the interposer, wherein the metal plate extends along a side surface of the outer portion of the interposer and the lower surface of the central portion of the interposer, and the metal plate has a cavity passing through a vicinity of a center of the metal plate planarly.
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