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    DUTY CYCLE ERROR ACCUMULATION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT HAVING THE SAME
    1.
    发明申请
    DUTY CYCLE ERROR ACCUMULATION CIRCUIT AND DUTY CYCLE CORRECTION CIRCUIT HAVING THE SAME 有权
    占空比误差累积电路和占空比校正电路

    公开(公告)号：US20140002157A1

    公开(公告)日：2014-01-02

    申请号：US13835824

    申请日：2013-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jong-Ryun CHOI ,  Ji-Hun OH ,  Choong-Bin LIM

    IPC: H03K3/017

    CPC classification number: H03K3/017 ,  H03K5/1565

    Abstract: A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal.

    Abstract translation: 占空比误差累积电路包括第一至第n延迟单元和反馈单元。 第一至第n延迟单元分别接收时钟信号，第一输入信号和第二输入信号，以通过基于逻辑电平延迟从第一和第二输入信号选择的一个信号来产生第一输出信号和第二输出信号 的时钟信号。 反馈单元基于第（k + 1）个延迟单元的第二输出信号向第k个延迟单元提供第二输入信号。 第k延迟单元的第一输出信号作为第一输入信号提供给第（k + 1）个延迟单元，并且时钟信号作为第一输入信号提供给第一延迟单元，并作为第二输入提供给第n延迟单元 信号。 占空比误差累积电路有效地校正时钟信号的占空比。

    DIGITAL MEASUREMENT CIRCUIT AND MEMORY SYSTEM USING THE SAME
    2.
    发明申请
    DIGITAL MEASUREMENT CIRCUIT AND MEMORY SYSTEM USING THE SAME 审中-公开

    公开(公告)号：US20200373919A1

    公开(公告)日：2020-11-26

    申请号：US16989074

    申请日：2020-08-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwan Yeob CHAE ,  Jong-Ryun CHOI

    IPC: H03K5/156 ,  G01R31/317 ,  H03K5/135 ,  H03K5/133

    Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

    SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS
    3.
    发明申请
    SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS 审中-公开

    公开(公告)号：US20190043841A1

    公开(公告)日：2019-02-07

    申请号：US16157642

    申请日：2018-10-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： KWANYEOB CHAE ,  Sanghoon JOO ,  Jong-Ryun CHOI ,  Jin-Ho CHOI

    IPC: H01L25/065 ,  H01L23/58 ,  H01L23/60 ,  H01L23/00 ,  H01L23/50

    Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.

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