-
公开(公告)号：US09032272B2
公开(公告)日：2015-05-12
申请号：US13690544
申请日：2012-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangyong Yoon , Kitae Park , Jinman Han
CPC classification number: G06F11/1068 , G06F11/1008 , G06F11/1072 , G11C29/52
Abstract: Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using, for example, an address-scrambled reprogramming technique.
Abstract translation: 操作存储器系统和非易失性存储器件的方法包括在从非易失性存储器件中的M位非易失性存储器单元的第一“源”部分读取的M页数据上执行错误校验和校正（ECC）操作，从而产生M页的 ECC处理的数据，其中M是大于2（2）的正整数。 然后使用例如地址加扰的重新编程技术，用非易失性存储器件中的M位非易失性存储单元的第二个“目标”部分用ECC处理数据的M页编程。
-
2.发明申请FLASH MEMORY DEVICES HAVING MULTI-BIT MEMORY CELLS THEREIN WITH IMPROVED READ RELIABILITY 审中-公开具有改善读取可靠性的多位存储器单元的闪存存储器件公开(公告)号：US20130286732A1
公开(公告)日：2013-10-31
申请号：US13920630
申请日：2013-06-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghyuk Chae , Jinman Han
IPC: G11C16/26
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3418
Abstract: Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.
Abstract translation: 集成电路存储器件包括非易失性N位存储器单元的阵列，其中N是大于1的整数。 还提供控制电路以可靠地从N位存储器单元读取数据。 电耦合到阵列的该控制电路被配置为确定存储在阵列中的所选N位存储器单元中的至少一位数据的值。 这是通过使用施加到所选择的N位存储器的对应的多个不等的读取电压来解码从所选择的N位存储器单元读取的至少一个硬数据值和多个软数据值（例如，6个数据值）来完成的 在读操作期间。
-
公开(公告)号：US20150248328A1
公开(公告)日：2015-09-03
申请号：US14695375
申请日：2015-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangyong Yoon , Kitae Park , Jinman Han
CPC classification number: G06F11/1068 , G06F11/1008 , G06F11/1072 , G11C29/52
Abstract: Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using an address-scrambled reprogramming technique, for example.
Abstract translation: 操作存储器系统和非易失性存储器件的方法包括在从非易失性存储器件中的M位非易失性存储器单元的第一“源”部分读取的M页数据上执行错误校验和校正（ECC）操作，从而产生M页的 ECC处理的数据，其中M是大于2（2）的正整数。 例如，非易失性存储器件中的M位非易失性存储单元的第二“目标”部分然后使用地址加扰的重新编程技术用ECC处理数据的M页被编程。
-
公开(公告)号：US10134476B2
公开(公告)日：2018-11-20
申请号：US15857898
申请日：2017-12-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dongsup Jin , Pilsang Yoon , Hong Rak Son , Junjin Kong , Young-Seop Shim , Jinman Han
IPC: G11C7/00 , G11C16/26 , G06F3/06 , G11C16/04 , G11C7/02 , G11C16/28 , G11C29/02 , G11C29/50 , G11C11/56 , G11C29/04
Abstract: A method for controlling a nonvolatile memory device includes requesting a plurality of first sampling values from the nonvolatile memory device, each of the first sampling values representing the number of memory cells having a threshold voltage between a first sampling read voltage and a second sampling read voltage. The first sampling values are processed through a non-linear filtering operation to estimate the number of memory cells having the threshold voltage between the first sampling read voltage and the second sampling read voltage.
-
5.发明授权公开(公告)号：US09378833B2
公开(公告)日：2016-06-28
申请号：US14788109
申请日：2015-06-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinman Han , Donghyuk Chae
CPC classification number: G11C16/16 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/26
Abstract: Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.
-
Patent Agency Ranking
6.发明授权Flash memory devices having multi-bit memory cells therein with improved read reliability 有权其中具有多位存储单元的闪存器件具有改进的可读性公开(公告)号：US09224489B2
公开(公告)日：2015-12-29
申请号：US13920630
申请日：2013-06-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Donghyuk Chae , Jinman Han
CPC classification number: G11C16/26 , G11C11/5642 , G11C16/0483 , G11C16/3418
Abstract: Integrated circuit memory devices include an array of nonvolatile N-bit memory cells, where N is an integer greater than one. Control circuitry is also provided to reliably read data from the N-bit memory cells. This control circuitry, which is electrically coupled to the array, is configured to determine, among other things, a value of at least one bit of data stored in a selected N-bit memory cell in the array. This is done by decoding at least one hard data value and a plurality of soft data values (e.g., 6 data values) read from the selected N-bit memory cell using a corresponding plurality of unequal read voltages applied to the selected N-bit memory cell during a read operation.
Abstract translation: 集成电路存储器件包括非易失性N位存储器单元的阵列，其中N是大于1的整数。 还提供控制电路以可靠地从N位存储器单元读取数据。 电耦合到阵列的该控制电路被配置为确定存储在阵列中的所选N位存储器单元中的至少一位数据的值。 这是通过使用施加到所选择的N位存储器的对应的多个不等的读取电压来解码从所选择的N位存储器单元读取的至少一个硬数据值和多个软数据值（例如，6个数据值）来完成的 在读操作期间。
-
公开(公告)号：US20140185389A1
公开(公告)日：2014-07-03
申请号：US14143154
申请日：2013-12-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youngjin Jeon , Jeongdon Ihm , Kilsoo Kim , Jinman Han
IPC: G11C7/10
CPC classification number: G06F3/0604 , G06F3/0656 , G06F3/0659 , G06F3/0679 , G11C7/04 , G11C7/1084 , G11C7/1093 , G11C7/1096 , G11C7/222 , H01L2224/48227 , H01L2924/181 , H01L2924/00012
Abstract: Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.
Abstract translation: 提供内存系统。 存储器系统可以包括多个非易失性存储器和被配置为控制多个非易失性存储器的存储器控制器。 此外，存储器系统可以包括连接在存储器控制器和多个非易失性存储器之间的输入/输出缓冲器电路。 数据通道可以连接在存储器控制器和输入/输出缓冲器电路之间，并且第一和第二内部数据通道可以连接在输入/输出缓冲器电路和多个非易失性存储器的相应的第一和第二组之间。 输入/输出缓冲器电路可以被配置为将数据信道连接到第一和第二内部数据信道之一。
-
公开(公告)号：US09280420B2
公开(公告)日：2016-03-08
申请号：US14695375
申请日：2015-04-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangyong Yoon , Kitae Park , Jinman Han
CPC classification number: G06F11/1068 , G06F11/1008 , G06F11/1072 , G11C29/52
Abstract: Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using an address-scrambled reprogramming technique, for example.
Abstract translation: 操作存储器系统和非易失性存储器件的方法包括在从非易失性存储器件中的M位非易失性存储器单元的第一“源”部分读取的M页数据上执行错误校验和校正（ECC）操作，从而产生M页的 ECC处理的数据，其中M是大于2（2）的正整数。 例如，非易失性存储器件中的M位非易失性存储单元的第二“目标”部分然后使用地址加扰的重新编程技术用ECC处理数据的M页被编程。
-
9.发明申请DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF 有权具有多位存储器件的数据存储系统及其操作方法公开(公告)号：US20140313824A1
公开(公告)日：2014-10-23
申请号：US14319137
申请日：2014-06-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
CPC classification number: G11C16/10 , G11C11/56 , G11C11/5628 , G11C14/0018 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
Abstract: A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory. The operating method of the data storage device includes storing data in the buffer memory, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the program pattern.
Abstract translation: 数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器的存储器控制器。 数据存储装置的操作方法包括将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是伴随存储器单元阵列的缓冲器程序操作的数据。 当存储在缓冲存储器中的数据是伴随缓冲器程序操作的数据时，该方法还包括确定是否需要对存储单元阵列执行主程序操作，并且当需要存储单元阵列的主程序操作时， 存储单元阵列中的主程序操作的程序模式。 该方法还包括基于该程序模式向存储单元阵列发出用于主程序操作的一组命令到多位存储器件。
-
公开(公告)号：US20130145234A1
公开(公告)日：2013-06-06
申请号：US13690544
申请日：2012-11-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangyong Yoon , Kitae Park , Jinman Han
IPC: G06F11/10
CPC classification number: G06F11/1068 , G06F11/1008 , G06F11/1072 , G11C29/52
Abstract: Methods of operating memory systems and nonvolatile memory devices include performing error checking and correction (ECC) operations on M pages of data read from a first “source” portion of M-bit nonvolatile memory cells within the nonvolatile memory device to thereby generate M pages of ECC-processed data, where M is a positive integer greater than two (2). A second “target” portion of M-bit nonvolatile memory cells within the nonvolatile memory device is then programmed with the M pages of ECC-processed data using an address-scrambled reprogramming technique, for example.
Abstract translation: 操作存储器系统和非易失性存储器件的方法包括在从非易失性存储器件中的M位非易失性存储器单元的第一“源”部分读取的M页数据上执行错误校验和校正（ECC）操作，从而产生M页的 ECC处理的数据，其中M是大于2（2）的正整数。 例如，非易失性存储器件中的M位非易失性存储单元的第二“目标”部分然后使用地址加扰的重新编程技术用ECC处理数据的M页被编程。
-
-
-
-
-
-
-
-
-
Search Results
12
records
(took 0.032 seconds)
