公开(公告)号：US10339989B2

公开(公告)日：2019-07-02

申请号：US15637099

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chaehoon Kim ,  Jin-Young Chun ,  Yunyeong Jeon

IPC: G11C7/12 ,  G11C5/14 ,  G11C7/10 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04

Abstract: A page buffer includes a pre-charge unit for pre-charging a bit line of a selected memory cell of a memory cell array via a first pre-charge line and pre-charging a sensing node via a second pre-charge line, during a pre-charge time, a bit line connection unit connected between the bit line and the sensing node and including a connecting node connected to the first pre-charge line, the bit line connection unit controlling a voltage of the sensing node, during a develop time, based on a bit line connection control signal and a sensing node voltage control signal, and a data input and output unit for generating sensing data by sensing a level of the voltage of the sensing node, during a sensing time.

公开(公告)号：US20240304263A1

公开(公告)日：2024-09-12

申请号：US18384681

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungsoo KIM ,  Minseo Cha ,  Jin-Young Chun

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/12

Abstract: The present disclosure provides methods and apparatuses for reducing a program voltage rising time. In some embodiments, a flash memory includes a memory cell array including a plurality of memory cells, a target voltage generator configured to adjust a target voltage level of a word line recovery voltage provided to the plurality of memory cells, and a word line voltage controller configured to provide recovery control signals for controlling the target voltage level of the word line recovery voltage. The target voltage generator is further configured to adjust the word line recovery voltage provided to a selected word line to the target voltage level, based on the recovery control signals provided during a word line recovery operation following a program verify operation, and to reduce a program voltage rising time in a program execution operation period of a next program loop by adjusting the target voltage level.

公开(公告)号：US12277995B2

公开(公告)日：2025-04-15

申请号：US17988797

申请日：2022-11-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Young Chun ,  Minjae Seo ,  Moosung Kim

IPC: G11C7/10 ,  G11C7/12 ,  G11C7/20

Abstract: A non-volatile memory device includes: a memory cell; a bit line connected to the memory cell; a first cross coupled inverter for storing data sensed from the memory cell through a sensing node connected to the bit line; a first transistor and a second transistor respectively connected to respective ends of the first cross coupled inverter and respectively transmitting a ground voltage to respective ends of the first cross coupled inverter; and a control circuit for operating the first transistor and the second transistor at least once for at least one of an initialize period in which the sensing node is discharged and a precharge period in which the bit line is precharged.

公开(公告)号：US10290343B2

公开(公告)日：2019-05-14

申请号：US15608219

申请日：2017-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： ChaeHoon Kim ,  Kyoman Kang ,  Tae-Hong Kwon ,  Taeyun Lee ,  Jin-Young Chun

IPC: G11C11/4091 ,  G11C5/14 ,  G11C7/06 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C7/12 ,  G11C13/00 ,  G11C16/04 ,  G11C27/02

Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.

公开(公告)号：US20180096718A1

公开(公告)日：2018-04-05

申请号：US15608219

申请日：2017-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： ChaeHoon KIM ,  Kyoman Kang ,  Tae-Hong Kwon ,  Taeyun Lee ,  Jin-Young Chun

IPC: G11C11/4091 ,  G11C7/12

CPC classification number: G11C11/4091 ,  G11C5/145 ,  G11C7/06 ,  G11C7/12 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/32 ,  G11C27/02 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.

公开(公告)号：US09502137B2

公开(公告)日：2016-11-22

申请号：US14205482

申请日：2014-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Yong Yoon ,  Kyung-Ryun Kim ,  Jin-Young Chun

IPC: G11C29/00 ,  G11C29/50 ,  G06F11/10 ,  G11C29/02 ,  H03M13/39 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C29/50004 ,  G06F11/1048 ,  G06F11/1068 ,  G11C11/56 ,  G11C16/34 ,  G11C29/026 ,  G11C29/028 ,  H03M13/3927

Abstract: In a method of optimizing a log likelihood ratio (LLR) used to correct errors related to data stored in a nonvolatile memory device, variation of threshold voltage distribution for a plurality of memory cells included in the nonvolatile memory device is monitored, and the LLR for the memory cells is updated based on a monitoring result. Although the characteristics of the memory cells are deteriorated, the LLR is continuously maintained to the optimal value.

Abstract translation: 在优化用于校正与存储在非易失性存储器件中的数据有关的误差的对数似然比（LLR）的方法中，监视非易失性存储器件中包括的多个存储器单元的阈值电压分布的变化，并且LLR用于 基于监视结果来更新存储器单元。 虽然存储单元的特性恶化，但是LLR连续地保持在最佳值。