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公开(公告)号：US11737271B2
公开(公告)日：2023-08-22
申请号：US16993570
申请日：2020-08-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Tae-Hong Kwon , Chan Ho Kim , Kyung Hwa Yun , Dae Seok Byeon , Chi Weon Yoon
CPC classification number: H10B43/27 , G11C5/145 , G11C16/08 , G11C16/24 , G11C16/32 , H10B43/35 , H10B43/40
Abstract: In order to permit dense integration of a high number of stacked word lines in the semiconductor memory device, a charge pump is included in the semiconductor memory device. The charge pump makes use of a capacitor. The capacitor is implemented with respect to the dense integration. Some components are placed under the stacked word lines, and some are not under the stacked word lines. The capacity of the capacitor not under the stacked word lines is provided in part by a parallel structure.
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Patent Agency Ranking
2.发明授权公开(公告)号：US12272409B2
公开(公告)日：2025-04-08
申请号：US18176347
申请日：2023-02-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Tae-Hong Kwon , Kiwhan Song , Gyosoo Choo
Abstract: Various example embodiments provide a flash memory device, comprising a cell string; a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by precharging a sensing node connected to the bit line; and a voltage regulator. The page buffer comprises a latch including first and second inverters coupled between a latch node and an inverted latch node; and a pull-down NMOS transistor for tripping the sensing result of the selected memory cell to the latch node. The voltage regulator adjusts a trip voltage by providing the source voltage to the pull-down NMOS transistor. The flash memory device reduce a trip voltage variation range by using only the pull-down NMOS transistor characteristics. Also, an OFF cell margin and an ON cell margin may be secured by adjusting the level of the trip voltage using the source voltage.
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公开(公告)号：US12272419B2
公开(公告)日：2025-04-08
申请号：US18217087
申请日：2023-06-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yeji Shin , Tae-Hong Kwon , Yoonjae Lee , Seokin Hong
Abstract: Disclosed is a charge pump of a flash memory, which includes a first stage pump that is connected between an output terminal and a first pump node, and a second stage pump that is connected between the first pump node and a second pump node. The first stage pump includes a first switch circuit that is connected between a power terminal and the first pump node and provides a power supply voltage to the first pump node in response to a first stage signal, in a normal operation, and a first pump circuit that generates a first pumping voltage by using a voltage of the first pump node in response to a first clock signal and provides the first pumping voltage to the output terminal. The first switch circuit blocks a current flow from the first pump node to the power terminal in a sudden power-off event.
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公开(公告)号：US10290343B2
公开(公告)日：2019-05-14
申请号：US15608219
申请日：2017-05-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： ChaeHoon Kim , Kyoman Kang , Tae-Hong Kwon , Taeyun Lee , Jin-Young Chun
IPC: G11C11/4091 , G11C5/14 , G11C7/06 , G11C16/24 , G11C16/26 , G11C16/32 , G11C7/12 , G11C13/00 , G11C16/04 , G11C27/02
Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.
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公开(公告)号：US20180096718A1
公开(公告)日：2018-04-05
申请号：US15608219
申请日：2017-05-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： ChaeHoon KIM , Kyoman Kang , Tae-Hong Kwon , Taeyun Lee , Jin-Young Chun
IPC: G11C11/4091 , G11C7/12
CPC classification number: G11C11/4091 , G11C5/145 , G11C7/06 , G11C7/12 , G11C16/0483 , G11C16/24 , G11C16/26 , G11C16/32 , G11C27/02 , G11C2013/0042 , G11C2013/0054
Abstract: Methods of operating a memory device include at least partially charging a sensing node within a page buffer of the memory device to a first precharge voltage, by sampling a trip voltage of a sensing latch within the page buffer. Thereafter, a voltage of the sensing node is boosted from the first precharge voltage to a higher second precharge voltage. Then, a voltage of the sensing node that reflects a value of data stored in a memory cell of the memory device is developed at the sensing node. The developed voltage is then transferred to the sensing latch so that data stored by the sensing latch reflects the value of data stored in the memory cell.
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6.发明授权Nonvolatile memory device, storage device having the same, operating method thereof 有权非易失性存储装置，具有其的存储装置，其操作方法公开(公告)号：US09570176B2
公开(公告)日：2017-02-14
申请号：US14668544
申请日：2015-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Won-Taeck Jung , Tae-Hong Kwon , Tae-Min Park , Ohsuk Kwon
Abstract: An operating method of a nonvolatile memory device includes determining whether a memory block is a selected block, and when the memory block is not the selected block, determining whether the memory block shares a block word line with the selected block. The method further includes applying an unselected block word line voltage to word lines of the memory block when the memory block shares the block word line with the selected block, and floating the word lines of the memory block when the memory block does not share the block word line with the selected block.
Abstract translation: 非易失性存储器件的操作方法包括确定存储器块是否是所选择的块，以及当存储器块不是所选择的块时，确定存储器块是否与所选择的块共享块字线。 该方法还包括当存储器块与所选择的块共享块字线时将未选择的块字线电压施加到存储器块的字线，并且当存储器块不共享块时浮置存储器块的字线 字线与所选块。
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