Abstract:
An image device may include a clock generator to generate a first output clock of a first frequency, a link layer to generate a control signal for changing the first frequency and output first parallel data including first frame information, a detector to generate a collision avoidance command to change the first frequency to a second frequency during a vertical blanking time, and a frequency changer to receive the collision avoidance command from the detector and transmit a frequency change command to the link layer. The link layer transmits the control signal to the clock generator based on the frequency change command. The vertical blanking time is a time period from a first time point at which the first parallel data is not output from the link layer to a second time point at which second parallel data is output.
Abstract:
A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.
Abstract:
A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.
Abstract:
A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.
Abstract:
An image sensor is provided which includes a plurality of unit pixels, ones of which are configured to convert an input light signal into at least four frame signals. The image sensor also includes a signal processor that is configured to measure a distance from an object based on the at least four frame signals from one of the plurality of unit pixels.
Abstract:
A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.
Abstract:
The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.
Abstract:
An image sensor includes a photo gate controller configured to generate a plurality of demodulated signals respectively corresponding to a plurality of rows of a pixel array and a photo gate driver configured to adjust a phase of the demodulated signals using a source clock signal to remove power, voltage and temperature (PVT) noise and to apply the phase-adjusted demodulated signals to the pixel array. The image sensor matches the phases of the respective demodulated signals using the source clock signal generated based on a reference clock signal, thereby increasing the quality of depth images.
Abstract:
A high-speed interface apparatus and method of correcting skew in the apparatus are provided. A high-speed transmitter includes a transmission D-PHY module that generates and transmits a clock signal through a clock channel, generates a deskew synchronous code and test data in response to a deskew request signal, transmits the deskew synchronous code followed by the test data through a data channel, and transmits a normal synchronous code followed by normal data through the data channel in normal mode.
Abstract:
The image sensor includes a first analog-to-digital converter configured to convert a first analog pixel signal output from a first pixel in a row into first digital signals, a second analog-to-digital converter configured to convert a second analog pixel signal output from a second pixel in the row into second digital signals, a first output circuit configured to output a first bit value at a first position in the first digital signals in response to a first enable control signal, and a second output circuit configured to output a second bit value at a second position in the second digital signals in response to a second enable control signal, the second position in the second digital signals corresponding to the first position in the first digital signals, wherein the second enable control signal is activated with a delay from the activation of the first enable control signal.