公开(公告)号：US20180294280A1

公开(公告)日：2018-10-11

申请号：US15913530

申请日：2018-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young KIM ,  Chang-beom KIM ,  Hyun-jeong ROH ,  Tae-joong SONG ,  Dal-hee LEE ,  Sung-we CHO

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US20180342505A1

公开(公告)日：2018-11-29

申请号：US16037581

申请日：2018-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1211

Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

公开(公告)号：US20170133380A1

公开(公告)日：2017-05-11

申请号：US15409523

申请日：2017-01-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-young KIM ,  Sung-we CHO ,  Tae-joong SONG ,  Sang-hoon BAEK

IPC: H01L27/092 ,  G06F17/50 ,  H01L27/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

公开(公告)号：US20200235126A1

公开(公告)日：2020-07-23

申请号：US16842867

申请日：2020-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ha-young KIM ,  Chang-beom Kim ,  Hyun-jeong Roh ,  Tae-joong Song ,  Dal-hee Lee ,  Sung-we Cho

IPC: H01L27/118 ,  H01L27/02

Abstract: An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

公开(公告)号：US20130262535A1

公开(公告)日：2013-10-03

申请号：US13904493

申请日：2013-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joo-young HWANG ,  Min-sung JANG ,  Jae-kyoung BAE ,  Ha-young KIM ,  Alexander KIRNASOV

IPC: G06F17/30

CPC classification number: G06F17/30091 ,  G06F17/3012 ,  G06F17/30138 ,  G06F17/30227

Abstract: A method of managing data of a file system using a database management system is provided. According to the method, the metadata of the file system is managed using a database management system (DBMS), but writing data to or reading data from a disk is directly performed by the file system according to the method directly performed not through other file systems or DBMSs. In this way, stable transactions are guaranteed for a user, and the user can design a disk allocation algorithm optimized with respect to a multimedia environment.

Abstract translation: 提供了一种使用数据库管理系统管理文件系统的数据的方法。 根据该方法，使用数据库管理系统（DBMS）来管理文件系统的元数据，但是根据直接不通过其他文件系统执行的方法，直接由文件系统执行向磁盘写入数据或从磁盘读取数据 或DBMS。 以这种方式，用户可以保证稳定的交易，并且用户可以设计针对多媒体环境优化的磁盘分配算法。

公开(公告)号：US20200294905A1

公开(公告)日：2020-09-17

申请号：US16886020

申请日：2020-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-gyum KIM ,  Ha-young KIM ,  Tae-joong SONG ,  Jong-hoon JUNG ,  Gi-young YANG ,  Jin-young LIM

IPC: H01L23/50 ,  H01L29/788 ,  H01L23/528 ,  H01L27/02 ,  H01L27/118

Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

公开(公告)号：US20200152627A1

公开(公告)日：2020-05-14

申请号：US16746071

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/02

Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.

公开(公告)号：US20190287891A1

公开(公告)日：2019-09-19

申请号：US16433092

申请日：2019-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-gyum KIM ,  Ha-young KIM ,  Tae-joong SONG ,  Jong-hoon JUNG ,  Gi-young YANG ,  Jin-young LIM

IPC: H01L23/50 ,  H01L29/788 ,  H01L27/118 ,  H01L27/02 ,  H01L23/528

Abstract: A standard cell of an IC includes a cell area including a transistor configured to determine a function of the standard cell; a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in a first direction; and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. The active area includes a first active area and a second active area spaced apart from each other in a second direction perpendicular to the first direction and extend parallel to each other in the first direction. At least one of the first active area and the second active area provided in the first dummy area is biased, and at least one of the first active area and the second active area provided in the second dummy area is biased.

公开(公告)号：US20180226336A1

公开(公告)日：2018-08-09

申请号：US15871206

申请日：2018-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-gyum KIM ,  Ha-young KIM ,  Tae-joong SONG ,  Jong-hoon JUNG ,  Gi-young YANG ,  Jin-young LIM

IPC: H01L23/50 ,  H01L29/788

CPC classification number: H01L23/50 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/788 ,  H01L2027/11831 ,  H01L2924/14

Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.