公开(公告)号：US20190123046A1

公开(公告)日：2019-04-25

申请号：US16230656

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAE-WANG LEE

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/10 ,  H01L29/423 ,  H01L29/08

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

公开(公告)号：US20210091074A1

公开(公告)日：2021-03-25

申请号：US17113787

申请日：2020-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAE-WANG LEE

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L23/535 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/51 ,  H01L29/786

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

公开(公告)号：US20170250180A1

公开(公告)日：2017-08-31

申请号：US15295115

申请日：2016-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAE-WANG LEE

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/51 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423 ,  H01L23/535

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/7831 ,  H01L29/785

Abstract: A semiconductor device includes a first active structure on a substrate including a first epitaxial pattern, a second epitaxial pattern and a first channel pattern between the first epitaxial pattern and the second epitaxial pattern, the first channel pattern including at least one channel pattern stacked on the substrate. A first gate structure is disposed on top and bottom surfaces of the first channel pattern. A second active structure on the substrate and includes the second epitaxial pattern, a third epitaxial pattern and a second channel pattern between the second epitaxial pattern and the third epitaxial pattern in the first direction. The second channel pattern includes at least one channel pattern stacked on the substrate. The number of stacked second channel patterns is greater than the number of stacked first channel patterns. A second gate structure is disposed on top and bottom surfaces of the second channel pattern.

公开(公告)号：US20230215868A1

公开(公告)日：2023-07-06

申请号：US18176463

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAE-SEOK YANG ,  HAE-WANG LEE

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L21/823878 ,  H01L2027/11864 ,  H01L2027/11861 ,  H01L2027/11829 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

公开(公告)号：US20200043945A1

公开(公告)日：2020-02-06

申请号：US16270214

申请日：2019-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HUN KIM ,  JAE-SEOK YANG ,  HAE-WANG LEE

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

公开(公告)号：US20180174953A1

公开(公告)日：2018-06-21

申请号：US15794131

申请日：2017-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEON-AH NAM ,  IKUO NAKAMATSU ,  DONG-HYUN KIM ,  CHUL-HONG PARK ,  YUN-SE OH ,  HAE-WANG LEE ,  HO-JUN CHOI

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/48 ,  H01L27/0886 ,  H01L29/6681 ,  H01L29/785 ,  H01L2924/13067

Abstract: A semiconductor device includes active fins on a substrate. Gate lines each extend in the second direction on the active fins. A contact plug is positioned on the active fins. A first via is in one of the first contact plugs. A first conductive line overlaps a first via. A first distance from a first active fin on which a first gate line of the gate lines is formed to an end of the first gate line is more than a predetermined distance. A second distance from a second active fin on which the first gate line is formed to the first active fin of the active fins is equal to or less than the predetermined distance. The second active fin is spaced apart from the first contact plugs to not overlap the first contact plugs.