公开(公告)号：US20210057284A1

公开(公告)日：2021-02-25

申请号：US17089822

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAESEOK YANG ,  HAEWANG LEE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

公开(公告)号：US20200144129A1

公开(公告)日：2020-05-07

申请号：US16439860

申请日：2019-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAESEOK YANG ,  HAEWANG LEE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/308

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

公开(公告)号：US20230215868A1

公开(公告)日：2023-07-06

申请号：US18176463

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAE-SEOK YANG ,  HAE-WANG LEE

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L21/823878 ,  H01L2027/11864 ,  H01L2027/11861 ,  H01L2027/11829 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

公开(公告)号：US20200043945A1

公开(公告)日：2020-02-06

申请号：US16270214

申请日：2019-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HUN KIM ,  JAE-SEOK YANG ,  HAE-WANG LEE

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.