公开(公告)号：US20160070848A1

公开(公告)日：2016-03-10

申请号：US14690073

申请日：2015-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-KWON KANG ,  JAE-SEOK YANG ,  SUNG-WOOK HWANG ,  DONG-GYUN KIM ,  JI-YOUNG JUNG

IPC: G06F17/50

CPC classification number: G03F1/70 ,  G03F7/70433 ,  G03F7/70466

Abstract: A method of decomposing a layout of a semiconductor device for a quadruple patterning technology (QPT) process includes dividing the layout of the semiconductor device into a first temporary pattern, which includes rectangular features having a rectangular shape, and a second temporary pattern, which includes cross couple features having a Z-shape, generating a third temporary pattern and a fourth temporary pattern by performing a pattern dividing operation on the first temporary pattern in a first direction, generating a first target pattern and a second target pattern by incorporating each of the cross couple features included in the second temporary pattern into one of the third temporary pattern and the fourth temporary pattern, and generating first through fourth decomposed patterns by performing the pattern dividing operation on the first target pattern and the second target pattern in a second direction.

Abstract translation: 分解用于四重图案形成技术（QPT）处理的半导体器件的布局的方法包括将半导体器件的布局划分成包括具有矩形形状的矩形特征和第二临时图案的第一临时图案，其包括 通过在第一方向上对第一临时图案执行图案划分操作，产生第三临时图案和第四临时图案的交叉耦合特征，通过将第一临时图案和第二临时图案中的每一个结合在一起，产生第一目标图案和第二目标图案 将包括在第二临时图案中的交叉耦合特征转换成第三临时图案和第四临时图案之一，并且通过对第一目标图案和第二目标图案沿第二方向执行图案划分操作来产生第一至第四分解图案。

公开(公告)号：US20230215868A1

公开(公告)日：2023-07-06

申请号：US18176463

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAE-SEOK YANG ,  HAE-WANG LEE

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L21/823878 ,  H01L2027/11864 ,  H01L2027/11861 ,  H01L2027/11829 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.

公开(公告)号：US20200043945A1

公开(公告)日：2020-02-06

申请号：US16270214

申请日：2019-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HUN KIM ,  JAE-SEOK YANG ,  HAE-WANG LEE

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02

Abstract: A semiconductor device includes a substrate having cell areas and power areas that are alternately arranged in a second direction. Gate structures extend in the second direction. The gate structures are spaced apart from each other in a first direction perpendicular to the second direction. Junction layers are arranged at both sides of each gate structure. The junction layers are arranged in the second direction such that each of the junction layer has a flat portion that is proximate to the power area. Cutting patterns are arranged in the power areas. The cutting patterns extend in the first direction such that each of the gate structures and each of the junction layers in neighboring cell areas are separated from each other by the cutting pattern.