公开(公告)号：US20210057284A1

公开(公告)日：2021-02-25

申请号：US17089822

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAESEOK YANG ,  HAEWANG LEE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

公开(公告)号：US20200144129A1

公开(公告)日：2020-05-07

申请号：US16439860

申请日：2019-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAESEOK YANG ,  HAEWANG LEE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/308

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.