公开(公告)号：US20210065809A1

公开(公告)日：2021-03-04

申请号：US16821225

申请日：2020-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohee HWANG ,  Taehun KIM ,  Minkyung BAE ,  Myunghun WOO ,  Bongyong LEE

IPC: G11C16/14 ,  G11C16/32 ,  G11C16/12 ,  G11C16/24 ,  G11C16/04

Abstract: A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

公开(公告)号：US20240427715A1

公开(公告)日：2024-12-26

申请号：US18588099

申请日：2024-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JOONHO JUN ,  Minwoo LEE ,  Byoungkon JO ,  Duksung KIM ,  Doohee HWANG

IPC: G06F13/16 ,  G06F13/40 ,  G11C11/42

Abstract: An optical memory module includes a substrate, a first memory controller on the substrate, and a plurality of first memory devices on the substrate. The first memory controller includes the first transceiver. The first transceiver receives a first optical input signal through a first optical interconnection or outputs a first optical output signal through the first optical interconnection. The first memory controller is optically connected to an optical logic module located outside the optical memory module through the first transceiver and the first optical interconnection. The plurality of first memory devices are controlled by the first memory controller and accessed by the optical logic module through the first memory controller, the first transceiver and the first optical interconnection.

公开(公告)号：US20220199150A1

公开(公告)日：2022-06-23

申请号：US17529900

申请日：2021-11-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Saemi SONG ,  Dokyun KIM ,  Yeonkyu CHOI ,  Doohee HWANG

IPC: G11C11/406

Abstract: Provided are a memory device and a method of refreshing the memory device regardless of a refresh rate multiplier for a temperature. In response to a refresh command at each base refresh rate (tREFi) based on a measured temperature, a memory device refreshes M memory cell rows at room temperature, refreshes 2M memory cell rows at a high temperature, and refreshes (½)M memory cell rows at a low temperature. The memory device refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a refresh command applied after n skipped base refresh rates, and refreshes (n+1)*M memory cell rows at a base refresh rate tREFi in response to a pulling-in refresh command.

公开(公告)号：US20250013366A1

公开(公告)日：2025-01-09

申请号：US18597373

申请日：2024-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYOUNGKON JO ,  Minwoo LEE ,  Joonho JUN ,  Duk Sung KIM ,  Doohee HWANG

IPC: G06F3/06

Abstract: There is provided a memory device including a content addressable memory physical layer connected to external data pads. During the write operation, the content addressable memory physical layer transmits a selected data pattern from among data patterns stored in a content addressable memory cell array as input data to selected memory cells of a memory cell array corresponding to an address received from external device based on first data received from the external data pads. During the read operation, the content addressable memory physical layer compares output data read from the memory cell array with the data patterns based on an address received from external device, and outputs content addressable memory address corresponding to data pattern matched by a result of the comparing as second data through the external data pads.

公开(公告)号：US20220216233A1

公开(公告)日：2022-07-07

申请号：US17702967

申请日：2022-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong LEE ,  Taehun KIM ,  Minkyung BAE ,  Myunghun WOO ,  Doohee HWANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11524

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

公开(公告)号：US20220157373A1

公开(公告)日：2022-05-19

申请号：US17399402

申请日：2021-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkyu CHOI ,  Dokyun KIM ,  Seongjin LEE ,  Doohee HWANG

IPC: G11C11/406 ,  G11C7/10

Abstract: A memory system includes a memory controller and a memory device. The memory controller generates refresh commands periodically by an average refresh interval. The memory device performs a normal refresh operation and a hammer refresh operation during a refresh cycle time. The memory device includes a memory cell array including memory cells connected to a plurality of wordlines, a temperature sensor configured to provide temperature information by measuring an operation temperature of the memory cell array and a refresh controller configured to control the normal refresh operation and the hammer refresh operation. The refresh controller varies a hammer ratio of a unit hammer execution number of the hammer refresh operation executed during the refresh cycle time with respect to a unit normal execution number of the normal refresh operation executed during the refresh cycle time.