公开(公告)号：US20210065809A1

公开(公告)日：2021-03-04

申请号：US16821225

申请日：2020-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doohee HWANG ,  Taehun KIM ,  Minkyung BAE ,  Myunghun WOO ,  Bongyong LEE

IPC: G11C16/14 ,  G11C16/32 ,  G11C16/12 ,  G11C16/24 ,  G11C16/04

Abstract: A semiconductor device includes a source layer; a plurality of channel structures; a plurality of gate electrodes; and a common source line. At least one of the plurality of gate electrodes provides a GIDL line. For an erasing operation, an erasing voltage applied to the common source line reaches a target voltage, and, after the erasing voltage reaches the target voltage, a step increment voltage is applied to the erasing voltage, such that the erasing voltage has a voltage level higher than a voltage level of the target voltage. After the step increment voltage has been applied for a desired time period, the voltage level of the erasing voltage is decreased to the target voltage level for the remainder of the erasing operation.

公开(公告)号：US20220216233A1

公开(公告)日：2022-07-07

申请号：US17702967

申请日：2022-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bongyong LEE ,  Taehun KIM ,  Minkyung BAE ,  Myunghun WOO ,  Doohee HWANG

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11524

Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.

公开(公告)号：US20200020717A1

公开(公告)日：2020-01-16

申请号：US16265688

申请日：2019-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： BONGYONG LEE ,  TAE HUN KIM ,  Minkyung BAE

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556

Abstract: A three-dimensional (3D) semiconductor memory device may include a stack structure including gate electrodes sequentially stacked on a substrate, and a vertical channel penetrating the stack structure. The gate electrodes may include a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, and an erase gate electrode, which are sequentially stacked on the substrate.

公开(公告)号：US20230194100A1

公开(公告)日：2023-06-22

申请号：US18099376

申请日：2023-01-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinkyum KIM ,  Changhyun SON ,  Hyunjeong KIM ,  Jeonghyun PARK ,  Minkyung BAE ,  Sungmin OH

IPC: F24C7/08 ,  F24C3/12

CPC classification number: F24C7/087 ,  F24C3/128 ,  F24C7/085

Abstract: An apparatus and method for cooking at a constant temperature in an oven including performing a temperature raising operation of operating at least one of at least one heater and at least one circulation fan until a temperature of a preset ratio of a set temperature is reached, continuing the operating at the set temperature for a preset period, and setting an operation level by considering a temperature of the oven at an end of a current period and a temperature of the oven at a start of the current period. The method includes performing a temperature maintaining operation of operating at least one of the at least one heater and the at least one circulation fan for one period according to the set operation level, and repeating the setting of the operation level and the temperature maintaining operation until cooking is completed.