公开(公告)号：US20240047550A1

公开(公告)日：2024-02-08

申请号：US18182426

申请日：2023-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki Heun LEE ,  Yong Seok KIM ,  Hyun Cheol KIM ,  Dae Won HA

IPC: H01L29/51 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/516 ,  H01L29/41725 ,  H01L29/78391

Abstract: Provided are semiconductor devices. The semiconductor device includes a substrate, a gate structure disposed on the substrate and extending in a first direction, and an active pattern spaced apart from the substrate in a second direction, extending in a third direction, and penetrating the gate structure, wherein the active pattern includes a two-dimensional material, the gate structure comprises a gate insulating layer, a lower gate conductive layer, a ferroelectric layer, and an upper gate conductive layer, which are sequentially stacked on the active pattern, the gate insulating layer includes hexagonal boron nitride (h-BN), and the ferroelectric layer includes a bilayer of a two-dimensional material.

公开(公告)号：US20210398948A1

公开(公告)日：2021-12-23

申请号：US17463650

申请日：2021-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min KIM ,  Dae Won HA

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US20210233995A1

公开(公告)日：2021-07-29

申请号：US17212847

申请日：2021-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min-Chul SUN ,  Dae Won HA ,  Dong Hoon HWANG ,  Jong Hwa BAEK ,  Jong Min JEON ,  Seung Mo HA ,  Kwang Yong YANG ,  Jae Young PARK ,  Young Su CHUNG

IPC: H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

公开(公告)号：US20200027870A1

公开(公告)日：2020-01-23

申请号：US16395691

申请日：2019-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Seok HA ,  Kyoung-Mi PARK ,  Hyun-Seung SONG ,  Keon Yong CHEON ,  Dae Won HA

IPC: H01L27/02 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A semiconductor device includes a first fin pattern and a second fin pattern in a NMOS region, each extending lengthwise along a first direction and separated by a first trench and a third fin pattern and a fourth fin pattern in a PMOS region, each extending lengthwise along the first direction in parallel with respective ones of the first fin pattern and the second fin pattern and separated by a second trench. First and second isolation layers are disposed in the first and second trenches, respectively. A first gate electrode extends lengthwise along a second direction transverse to the first direction and crosses the first fin pattern. A second gate electrode extends lengthwise along the second direction and crosses the second fin pattern. Spaced apart third and fourth gate electrodes extend lengthwise along the second direction on the second isolation layer.

公开(公告)号：US20250098180A1

公开(公告)日：2025-03-20

申请号：US18829396

申请日：2024-09-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Nam KIM ,  Dae Won HA ,  Dong Guk CHO

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: There is provided a semiconductor device manufactured using a method that reduces a manufacturing time and cost of the semiconductor device. The semiconductor device includes a first semiconductor device module including: a first lower bonding pad; a second lower bonding pad; first upper bonding pads; and a memory cell disposed at a height level higher than a height level of each of the first and second lower bonding pads and lower than a height level of the first upper bonding pads. The semiconductor device further comprises a second semiconductor device module including second bonding pads and a transistor electrically connected to at least one of the second bonding pads; and a third semiconductor device module including third bonding pads. The third pads are spaced apart from the first and second lower bonding pads in a first direction. The first lower bonding pad contacts at least one of the second bonding pads. At least one of the third bonding pads contacts at least one of the first upper bonding pads. The first semiconductor device module includes a bonding pad connection plug directly electrically connecting the first lower bonding pad and at least one of the first upper bonding pads to each other.

公开(公告)号：US20230307423A1

公开(公告)日：2023-09-28

申请号：US18328389

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min KIM ,  Dae Won HA

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L23/481 ,  H01L21/76898 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/80894 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06593 ,  H01L2224/08145

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US20200066683A1

公开(公告)日：2020-02-27

申请号：US16508857

申请日：2019-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min KIM ,  Dae Won HA

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L25/00

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US20190189804A1

公开(公告)日：2019-06-20

申请号：US16044691

申请日：2018-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Gun YOU ,  Dong Hyun KIM ,  Byoung-Gi KIM ,  Yun Suk NAM ,  Yeong Min JEON ,  Sung Chul PARK ,  Dae Won HA

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L29/7855 ,  H01L21/762 ,  H01L21/823821 ,  H01L21/823864 ,  H01L23/5329 ,  H01L29/0642 ,  H01L29/6681

Abstract: A semiconductor device includes first and second fin patterns on a substrate and extending apart from each other, a field insulating film on the substrate and surrounding parts of the first and second fin patterns, a first gate structure on the first fin pattern and intersecting the first fin pattern, a second gate structure on the second fin pattern and intersecting the second fin pattern, and a separating structure protruding from a top surface of the field insulating film and separating the first and second gate structures, the field insulating film and the separating structure including a same insulating material.

公开(公告)号：US20250022876A1

公开(公告)日：2025-01-16

申请号：US18901283

申请日：2024-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min KIM ,  Dae Won HA

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/822 ,  H01L23/528 ,  H01L27/088 ,  H01L27/146 ,  H01L29/417 ,  H01L29/78

Abstract: A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.

公开(公告)号：US20220352342A1

公开(公告)日：2022-11-03

申请号：US17838573

申请日：2022-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guk Il AN ,  Keun Hwi CHO ,  Dae Won HA ,  Seung Seok HA

IPC: H01L29/51 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L49/02

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate and a first conductive connection group on the gate structure. The gate structure includes a gate spacer and a gate electrode. The first conductive connection group includes a ferroelectric material layer. At least a part of the ferroelectric material layer is disposed above an upper surface of the gate spacer. And the ferroelectric material layer forms a ferroelectric capacitor having a negative capacitance in the first conductive connection group.