公开(公告)号：US20170255575A1

公开(公告)日：2017-09-07

申请号：US15233850

申请日：2016-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4068 ,  G06F13/42

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20180239711A1

公开(公告)日：2018-08-23

申请号：US15953397

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Craig HANSON ,  Ian SWARBRICK ,  Michael BEKERMAN ,  Chihjen CHANG

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F12/0246 ,  G06F2212/1004 ,  G06F2212/1044 ,  G06F2212/657 ,  G06F2212/7201

Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.

公开(公告)号：US20200167297A1

公开(公告)日：2020-05-28

申请号：US16777206

申请日：2020-01-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  lndong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module includes: a non-volatile memory; and an asynchronous memory interface to interface with a memory controller. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20170365305A1

公开(公告)日：2017-12-21

申请号：US15231629

申请日：2016-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Craig HANSON ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

IPC: G11C7/10 ,  G06F1/32

CPC classification number: G11C7/1072 ,  G06F1/32 ,  G06F1/3234 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/04 ,  G11C5/148 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4074 ,  G11C2207/2227 ,  Y02D10/14 ,  Y02D50/20

Abstract: A memory module includes a plurality of memory components, an in-memory power manager, and an interface to a host computer over a memory bus. The in-memory power manager is configured to control a transition of a power state of the memory module. The transition of the power state of the memory module includes a direct transition from a low power down state to a maximum power down state.

公开(公告)号：US20250036584A1

公开(公告)日：2025-01-30

申请号：US18918046

申请日：2024-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20220358060A1

公开(公告)日：2022-11-10

申请号：US17872987

申请日：2022-07-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dimin NIU ,  Mu-Tien CHANG ,  Hongzhong ZHENG ,  Sun Young LIM ,  lndong KIM ,  Jangseok CHOI ,  Craig HANSON

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: A memory module that includes a non-volatile memory and an asynchronous memory interface to interface with a memory controller is presented. The asynchronous memory interface may use repurposed pins of a double data rate (DDR) memory channel to send an asynchronous data to the memory controller. The asynchronous data may be device feedback indicating a status of the non-volatile memory.

公开(公告)号：US20170109101A1

公开(公告)日：2017-04-20

申请号：US14970008

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Craig HANSON ,  Michael BEKERMAN ,  Siamack HAGHIGHI ,  Chihjen CHANG

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0652 ,  G06F3/0685 ,  G06F3/0688

Abstract: A memory module includes a solid-state drive (SSD) and a memory controller. The memory controller receives information from a host memory controller via a synchronous memory channel and determines to initiate background tasks of the SSD based on memory commands and a state of the memory module. According to one embodiment, the synchronous memory channel is a DRAM memory channel, and the SSD includes a flash memory. The background tasks of the SSD such as garbage collection, wear leveling, and erase block preparation are initiated during an idle state of the memory module.