知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.024 seconds)

    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY
    3.
    发明申请
    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY 有权

    公开(公告)号：US20220229551A1

    公开(公告)日：2022-07-21

    申请号：US17713228

    申请日：2022-04-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

    IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY SYSTEM
    7.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY SYSTEM 有权

    公开(公告)号：US20220172753A1

    公开(公告)日：2022-06-02

    申请号：US17409064

    申请日：2021-08-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun Young LIM ,  Seung Yong SHIN ,  Hyun Duk CHO

    IPC: G11C7/10 ,  G11C7/22

    Abstract: A memory device including a plurality of nonvolatile memory chips each including a status output pin and a buffer chip configured to receive a plurality of internal state signals, which indicate states of the plurality of nonvolatile memory chips, from the status output pins and output an external state signal having a set period on the basis of the internal state signals indicating a particular state, wherein in a first section of the external state signal having the set period, a duty cycle of the external state signal determines depending on an identification (ID) of the nonvolatile memory chip which outputs the internal state signal indicating the particular state among the plurality of nonvolatile memory chips.

    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY
    8.
    发明申请
    COORDINATED IN-MODULE RAS FEATURES FOR SYNCHRONOUS DDR COMPATIBLE MEMORY 审中-公开

    公开(公告)号：US20200218447A1

    公开(公告)日：2020-07-09

    申请号：US16819032

    申请日：2020-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Mu-Tien CHANG ,  Dimin NIU ,  Hongzhong ZHENG ,  Sun Young LIM ,  Indong KIM ,  Jangseok CHOI

    IPC: G06F3/06 ,  G11C29/52 ,  G06F11/10

    Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

    MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY SYSTEM
    10.
    发明公开
    MEMORY DEVICE, MEMORY SYSTEM, AND OPERATING METHOD OF MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240062790A1

    公开(公告)日：2024-02-22

    申请号：US18384973

    申请日：2023-10-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun Young LIM ,  Seung Yong SHIN ,  Hyun Duk CHO

    IPC: G11C7/10 ,  G11C7/22

    CPC classification number: G11C7/1063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C7/222

    Abstract: A memory device including a plurality of nonvolatile memory chips each including a status output pin and a buffer chip configured to receive a plurality of internal state signals, which indicate states of the plurality of nonvolatile memory chips, from the status output pins and output an external state signal having a set period on the basis of the internal state signals indicating a particular state, wherein in a first section of the external state signal having the set period, a duty cycle of the external state signal determines depending on an identification (ID) of the nonvolatile memory chip which outputs the internal state signal indicating the particular state among the plurality of nonvolatile memory chips.

Patent Agency Ranking