公开(公告)号：US20160363986A1

公开(公告)日：2016-12-15

申请号：US14735119

申请日：2015-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ian SWARBRICK ,  Michael BEKERMAN ,  Rohit NATARAJAN

IPC: G06F1/32 ,  G06F1/26 ,  G06F13/42

CPC classification number: G06F13/4282 ,  G06F1/3206 ,  G06F1/3253 ,  G06F1/3287 ,  Y02D10/151 ,  Y02D10/171

Abstract: A system and a method select a datapath through a meshed Input/Output (IO) fabric. A plurality of port controllers is coupled to interconnection logic. Each port controller is coupled to a corresponding communication link and outputs a detection signal if the corresponding communication link transitions from a first lower-power state to a second higher power state. The interconnection logic, responsive to the detection signal, is configured to output a first signal to one or more selected port controllers to transition the corresponding communication link coupled to the selected port controller from the first power state to the second power state based on a frequency of use of a datapath between the communication link corresponding to the port controller outputting the detection signal and the communication link corresponding to each of the one or more selected port controllers.

Abstract translation: 系统和方法通过网格输入/输出（IO）结构选择数据路径。 多个端口控制器耦合到互连逻辑。 如果对应的通信链路从第一低功率状态转换到第二较高功率状态，则每个端口控制器耦合到对应的通信链路并输出检测信号。 互连逻辑响应于检测信号被配置为将第一信号输出到一个或多个选择的端口控制器，以将耦合到所选端口控制器的对应通信链路从第一功率状态转换到第二功率状态，基于频率 在与输出检测信号的端口控制器相对应的通信链路与对应于一个或多个所选端口控制器中的每一个的通信链路之间使用数据路径。

公开(公告)号：US20170109101A1

公开(公告)日：2017-04-20

申请号：US14970008

申请日：2015-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Craig HANSON ,  Michael BEKERMAN ,  Siamack HAGHIGHI ,  Chihjen CHANG

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0616 ,  G06F3/0652 ,  G06F3/0685 ,  G06F3/0688

Abstract: A memory module includes a solid-state drive (SSD) and a memory controller. The memory controller receives information from a host memory controller via a synchronous memory channel and determines to initiate background tasks of the SSD based on memory commands and a state of the memory module. According to one embodiment, the synchronous memory channel is a DRAM memory channel, and the SSD includes a flash memory. The background tasks of the SSD such as garbage collection, wear leveling, and erase block preparation are initiated during an idle state of the memory module.

公开(公告)号：US20180239711A1

公开(公告)日：2018-08-23

申请号：US15953397

申请日：2018-04-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Craig HANSON ,  Ian SWARBRICK ,  Michael BEKERMAN ,  Chihjen CHANG

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F12/0246 ,  G06F2212/1004 ,  G06F2212/1044 ,  G06F2212/657 ,  G06F2212/7201

Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.