公开(公告)号：US09190357B2

公开(公告)日：2015-11-17

申请号：US14705416

申请日：2015-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Hyun Lee ,  Hoon Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/525 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/5252 ,  G11C5/04 ,  G11C29/883 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

公开(公告)号：US11910593B2

公开(公告)日：2024-02-20

申请号：US17032655

申请日：2020-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon Young Choi ,  Seung Jin Kim ,  Byung-Hyun Lee ,  Sang Jae Park

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H10B12/00 ,  G11C5/10 ,  G11C11/402 ,  H01L49/02

CPC classification number: H10B12/34 ,  G11C5/10 ,  G11C11/4023 ,  H01L28/91

Abstract: A semiconductor device may comprise: a plurality of lower electrodes which are on a substrate; a first electrode support which is between adjacent lower electrodes and comprises a metallic material; a dielectric layer which is on the lower electrodes and the first electrode support to extend along profiles of the first electrode support and each of the lower electrodes; and an upper electrode which is on the dielectric layer.

公开(公告)号：US11217457B2

公开(公告)日：2022-01-04

申请号：US16863244

申请日：2020-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjin Kim ,  Byung-Hyun Lee ,  Yoonyoung Choi ,  Tae-Kyu Kim ,  Heesook Cheon ,  Bo-Wo Choi ,  Hyun-Sil Hong

IPC: H01L21/311 ,  H01L21/027 ,  H01L21/48

Abstract: A method of fabricating a semiconductor device including preparing a substrate including a wafer inner region and a wafer edge region, the wafer inner region including a chip region and a scribe lane region, sequentially stacking a mold layer and a supporting layer on the substrate, forming a first mask layer on the supporting layer, the first mask layer including a first stepped region on the wafer edge region, forming a step-difference compensation pattern on the first stepped region, forming a second mask pattern including openings, on the first mask layer and the step-difference compensation pattern, and sequentially etching the first mask layer, the supporting layer, and the mold layer using the second mask pattern as an etch mask to form a plurality of holes in at least the mold layer may be provided.