FAN-OUT SEMICONDUCTOR PACKAGE
    1.
    发明申请

    公开(公告)号:US20180240751A1

    公开(公告)日:2018-08-23

    申请号:US15710374

    申请日:2017-09-20

    Abstract: A fan-out semiconductor package includes: a semiconductor chip; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on an active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip. The redistribution layer includes a line pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width, greater than the first line width, a fan-in region is a projected surface of the semiconductor chip projected in a direction perpendicular to the active surface, a fan-out region is a region surrounding the fan-in region, and the second line portion at least passes through a boundary between the fan-in region and the fan-out region.

    FAN-OUT SEMICONDUCTOR PACKAGE
    3.
    发明申请

    公开(公告)号:US20180323119A1

    公开(公告)日:2018-11-08

    申请号:US16036209

    申请日:2018-07-16

    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.

    FAN-OUT SEMICONDUCTOR PACKAGE
    5.
    发明申请

    公开(公告)号:US20180082962A1

    公开(公告)日:2018-03-22

    申请号:US15459322

    申请日:2017-03-15

    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, and the encapsulant fills spaces between walls of the through-hole and side surfaces of the semiconductor chip, and at least portions of the encapsulant extend to a space between the first interconnection member and the second interconnection member and a space between the active surface of the semiconductor chip and the second interconnection member.

    FAN-OUT SEMICONDUCTOR PACKAGE
    6.
    发明申请

    公开(公告)号:US20170365566A1

    公开(公告)日:2017-12-21

    申请号:US15377402

    申请日:2016-12-13

    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.

    FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE FAN-OUT SEMICONDUCTOR

    公开(公告)号:US20180122759A1

    公开(公告)日:2018-05-03

    申请号:US15632138

    申请日:2017-06-23

    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole, the semiconductor chip having an active surface with connection pads disposed thereon and the semiconductor chip having an inactive surface opposing the active surface, an encapsulant, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip, wherein the first connection member and the second connection member include redistribution layers electrically connected to the connection pads, wherein the semiconductor chip includes a first passivation layer disposed on the active surface and the semiconductor chip includes a second passivation layer disposed on the first passivation layer, and wherein the redistribution layer of the second connection member is directly formed on one surface of the second passivation layer and extends onto one surface of the first connection member.

    FAN-OUT SEMICONDUCTOR PACKAGE
    8.
    发明申请

    公开(公告)号:US20170278812A1

    公开(公告)日:2017-09-28

    申请号:US15381635

    申请日:2016-12-16

    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip.

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