公开(公告)号：US20180190602A1

公开(公告)日：2018-07-05

申请号：US15905062

申请日：2018-02-26

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Doo Hwan LEE ,  Jong Rip KIM ,  Hyoung Joon KIM ,  Jin Yul KIM ,  Kyung Seob OH

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.

公开(公告)号：US20170365566A1

公开(公告)日：2017-12-21

申请号：US15377402

申请日：2016-12-13

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Doo Hwan LEE ,  Jong Rip KIM ,  Hyoung Joon KIM ,  Jin Yul KIM ,  Kyung Seob OH

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip; and a passivation layer disposed on the second interconnection member. The first interconnection member and the second interconnection member include, respectively, redistribution layers electrically connected to the connection pads of the semiconductor chip, the second interconnection member includes an insulating layer on which the redistribution layer of the second interconnection member is disposed, and the passivation layer has a modulus of elasticity greater than that of the insulating layer of the second interconnection member.