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公开(公告)号:US20250142907A1
公开(公告)日:2025-05-01
申请号:US18643087
申请日:2024-04-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Changhyun KIM , Kyung-Eun BYUN , Minsu SEOL , Junyoung KWON , Huije RYU , Eunkyu LEE , Yeonchoo CHO
Abstract: A semiconductor device may include a substrate, a vertical channel, a gate electrode, and a conductive layer. The vertical channel may have a tube shape extending in a direction perpendicular to a surface of the substrate. The gate electrode may face the vertical channel with an outer insulating layer therebetween on an outer circumferential surface of the vertical channel. The conductive layer may face the vertical channel with an inner insulating layer therebetween on an inner circumferential surface of the vertical channel.
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2.
公开(公告)号:US20240030294A1
公开(公告)日:2024-01-25
申请号:US18321275
申请日:2023-05-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Minsu SEOL , Junyoung KWON , Jitak NAM , Minseok Yoo
IPC: H01L29/18 , H01L29/16 , H01L29/417 , H01L21/02
CPC classification number: H01L29/18 , H01L29/1606 , H01L29/41725 , H01L21/02568 , H01L21/02485
Abstract: A semiconductor device may include at least one first two-dimensional material layer; a source electrode and a drain electrode that are respectively on both sides of the at least one first two-dimensional material layer; second two-dimensional material layers respectively on a side of the source electrode and a side of the drain electrode and connected to the at least one first two-dimensional material layer; a gate insulating layer surrounding the at least one first two-dimensional material layer; and a gate electrode on the gate insulating layer.
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3.
公开(公告)号:US20230275128A1
公开(公告)日:2023-08-31
申请号:US18154978
申请日:2023-01-16
Inventor: Junyoung KWON , Sangwoo KIM , Kyung-Eun BYUN , Minsu SEOL , Minseok SHIN , Pin ZHAO , Taehyeong KIM , Jaehwan JUNG
CPC classification number: H01L29/18 , H01L29/66969
Abstract: A semiconductor device including a two-dimensional material and a method of manufacturing the same are provided. The semiconductor device may include a first two-dimensional material layer including a first two-dimensional semiconductor material; a plurality of second two-dimensional material layers connected to the first two-dimensional material layer, each having a thickness greater than that of the first two-dimensional material layer, and including a doped two-dimensional semiconductor material; and a plurality of electrodes on the plurality of second two-dimensional material layers.
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公开(公告)号:US20250126886A1
公开(公告)日:2025-04-17
申请号:US18917227
申请日:2024-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kyung-Eun BYUN , Minsu SEOL , Junyoung KWON , Huije RYU
IPC: H01L27/092 , H01L29/24 , H01L29/76 , H01L29/786
Abstract: Provided is a semiconductor device including a two-dimensional (2D) material. The semiconductor device may include a first channel including a first 2D material layer, a second channel apart from the first channel in a first direction and including a second 2D material layer, a common gate electrode between the first channel and the second channel, a first electrode and a second electrode apart from each other and respectively in contact with the first channel and the second channel, and a common electrode apart from the first electrode and the second electrode in a second direction intersecting the first direction and in contact with the first channel and the second channel. One of the first channel and the second channel may be an n-type channel and the other one may be a p-type channel.
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公开(公告)号:US20240304699A1
公开(公告)日:2024-09-12
申请号:US18591799
申请日:2024-02-29
Inventor: Junyoung KWON , Gwanhyung LEE , Heeje RYU
IPC: H01L29/49 , H01L29/04 , H01L29/24 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/786
CPC classification number: H01L29/4908 , H01L29/408 , H01L29/42384 , H01L29/66969 , H01L29/04 , H01L29/24 , H01L29/78648
Abstract: A semiconductor device includes a semiconductor layer including a two-dimensional semiconductor material, a source electrode and a drain electrode electrically connected to respective edge regions on the semiconductor layer, an insulating layer arranged on the semiconductor layer, and a gate electrode arranged on the insulating layer, wherein the insulating layer may include a single-crystal layer.
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6.
公开(公告)号:US20240170562A1
公开(公告)日:2024-05-23
申请号:US18366366
申请日:2023-08-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junyoung KWON , Minsu SEOL , Kyung-Eun BYUN , Changseok LEE , Minseok YOO
CPC classification number: H01L29/7606 , H01L29/24 , H01L29/66969
Abstract: A semiconductor device may include a first two-dimensional (2D) material layer, a second 2D material layer, a first electrode, a second electrode, a third electrode, a first gate electrode. and a second gate electrode. A Fermi-level may be pinned on an interfacial surface between the first 2D material layer and the first electrode. The Fermi-level may be depinned on an interfacial surface between the second 2D material layer and the first electrode.
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公开(公告)号:US20230112883A1
公开(公告)日:2023-04-13
申请号:US17690376
申请日:2022-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor: Minsu SEOL , Keunwook SHIN , Junyoung KWON , Minseok YOO , Changseok LEE
Abstract: Provided are a two-dimensional material structure, a semiconductor device including the two-dimensional material structure, and a method of manufacturing the semiconductor device. The two-dimensional material structure may include a first insulator including a first dielectric material; a second insulator on the first insulator and including a second dielectric material; a first two-dimensional material film on an exposed surface of the first insulator; and a second two-dimensional material film provided on an exposed surface of the second insulator. The first and second two-dimensional material films may include a two-dimensional material having a two-dimensional layered structure, and the second two-dimensional material film may include more layers of the two-dimensional material than the first two-dimensional material film.
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8.
公开(公告)号:US20230061267A1
公开(公告)日:2023-03-02
申请号:US17673239
申请日:2022-02-16
Applicant: Samsung Electronics Co., Ltd.
Inventor: Junyoung KWON , Minsu SEOL , Hyeonjin SHIN , Minseok YOO
IPC: H01L29/06 , H01L29/10 , H01L29/16 , H01L29/24 , H01L29/786 , H01L29/417 , H01L29/66 , H01L29/40
Abstract: An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.
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公开(公告)号:US20220406911A1
公开(公告)日:2022-12-22
申请号:US17545373
申请日:2021-12-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Minseok YOO , Minsu SEOL , Junyoung KWON , Kyung-Eun BYUN , Hyeonjin SHIN , Van Luan NGUYEN
IPC: H01L29/423 , H01L29/43
Abstract: Disclosed are an electronic device including a two-dimensional material, and a method of fabricating the electronic device. The electronic device may include a first metal layer including a transition metal, a second metal layer on the first metal layer and including gold (Au), and a two-dimensional material layer between the first metal layer and the second metal layer. The two-dimensional material layer may include a transition metal dichalcogenide (TMD). The two-dimensional material layer may be formed as a chalcogen element diffuses into the second metal layer and reacts with the transition metal of the first metal layer adjacent to the second metal layer.
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公开(公告)号:US20250142874A1
公开(公告)日:2025-05-01
申请号:US18660936
申请日:2024-05-10
Applicant: Samsung Electronics Co., Ltd.
Inventor: Changhyun KIM , Kyung-Eun BYUN , Minsu SEOL , Junyoung KWON , Huije RYU , Eunkyu LEE , Yeonchoo CHO
IPC: H01L29/78 , H01L27/092 , H01L29/10 , H01L29/66
Abstract: Provided is a semiconductor device including a substrate, a first vertical channel, a spacer, and a second vertical channel. The first vertical channel may have a sheet shape extending in a direction perpendicular to a surface of the substrate. The spacer may be provided at an end of the first vertical channel in an extension direction. The second vertical channel may be aligned with the first vertical channel on the spacer and have a sheet shape extending in a vertical direction.
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