公开(公告)号：US10459853B2

公开(公告)日：2019-10-29

申请号：US15628960

申请日：2017-06-21

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Wongyu Shin ,  Leesup Kim ,  Youngsuk Moon ,  Yongkee Kwon ,  Jaemin Jang

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/36

Abstract: A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

公开(公告)号：US11113210B2

公开(公告)日：2021-09-07

申请号：US16574386

申请日：2019-09-18

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Wongyu Shin ,  Leesup Kim ,  Youngsuk Moon ,  Yongkee Kwon ,  Jaemin Jang

IPC: G06F13/16 ,  G06F12/02 ,  G06F3/06 ,  G06F13/36 ,  G06F12/06

Abstract: A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

公开(公告)号：US11113211B2

公开(公告)日：2021-09-07

申请号：US16574425

申请日：2019-09-18

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Wongyu Shin ,  Leesup Kim ,  Youngsuk Moon ,  Yongkee Kwon ,  Jaemin Jang

IPC: G06F13/16 ,  G06F12/02 ,  G06F3/06 ,  G06F13/36 ,  G06F12/06

Abstract: A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

公开(公告)号：US10782914B2

公开(公告)日：2020-09-22

申请号：US16003927

申请日：2018-06-08

Applicant: SK hynix Inc.

Inventor： Seunggyu Jeong ,  Jung Hyun Kwon ,  Wongyu Shin ,  Do-Sun Hong

IPC: H04L12/28 ,  G06F3/06

Abstract: A buffer system may include a buffer configured to receive input data having an assigned priority level, store the input data within a memory stack regardless of the priority level assigned to the input data, and sequentially output the input data stored in the memory stack in order of the priority levels assigned to the input data.

公开(公告)号：US11036597B2

公开(公告)日：2021-06-15

申请号：US16212302

申请日：2018-12-06

Applicant: SK hynix Inc.

Inventor： Wongyu Shin ,  Jung Hyun Kwon ,  Seunggyu Jeong ,  Do Sun Hong

IPC: G06F11/00 ,  G06F11/20 ,  G06F11/10 ,  G11C29/52

Abstract: A semiconductor memory system includes a memory medium and a data input/output (I/O) pin repair control circuit. The memory medium includes a plurality of memory dies and a spare die. Each of the plurality of memory dies has a plurality of memory regions and a plurality of data I/O pins, and the spare die has a plurality of spare regions and a plurality of data I/O pins. The data I/O pin repair control circuit performs a repair process for replacing an abnormal data I/O pin among the plurality of data I/O pins included in any of the plurality of memory dies with a data I/O pin of the plurality of data I/O pins included in the spare die.

公开(公告)号：US20190385693A1

公开(公告)日：2019-12-19

申请号：US16203362

申请日：2018-11-28

Applicant: SK hynix Inc.

Inventor： Wongyu Shin ,  Jung Hyun Kwon ,  Seunggyu Jeong ,  Do Sun Hong

IPC: G11C29/42 ,  G06F11/10 ,  G11C11/409 ,  G11C11/16 ,  H03M13/11

Abstract: A memory system includes a memory medium and a memory controller. The memory medium includes data symbols and parity symbols which are respectively disposed at cross points of a plurality rows and a plurality of columns. The memory controller includes an error correction code (ECC) engine that is designed to execute an error correction operation at a fixed error correction level while the memory controller accesses the memory medium. The memory controller performs the error correction operation at the fixed error correction level using the ECC engine in a first error correction mode. The memory controller performs the error correction operation at an error correction level higher than the fixed error correction level using the ECC engine in a second error correction mode.

公开(公告)号：US11037610B2

公开(公告)日：2021-06-15

申请号：US16210303

申请日：2018-12-05

Applicant: SK hynix Inc.

Inventor： Seunggyu Jeong ,  Jung Hyun Kwon ,  Wongyu Shin ,  Do Sun Hong

IPC: G11C7/22 ,  G11C16/32 ,  G11C16/26 ,  G06F9/30 ,  G06F11/07 ,  G06F11/30 ,  G11C7/10

Abstract: A read time-out manager may include a counter and a plurality of timers. The counter may generate a counter output signal based on a first cycle time. The plurality of timers may be each configured to be assigned a read identification to measure a time-out period corresponding to the read identification. Each of the plurality of timers may operate in synchronization with the counter output signal to generate a time-out signal based on a second cycle time different from the first cycle time.