公开(公告)号：US11113211B2

公开(公告)日：2021-09-07

申请号：US16574425

申请日：2019-09-18

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Wongyu Shin ,  Leesup Kim ,  Youngsuk Moon ,  Yongkee Kwon ,  Jaemin Jang

IPC: G06F13/16 ,  G06F12/02 ,  G06F3/06 ,  G06F13/36 ,  G06F12/06

Abstract: A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

公开(公告)号：US10459853B2

公开(公告)日：2019-10-29

申请号：US15628960

申请日：2017-06-21

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Wongyu Shin ,  Leesup Kim ,  Youngsuk Moon ,  Yongkee Kwon ,  Jaemin Jang

IPC: G06F13/16 ,  G06F3/06 ,  G06F13/36

Abstract: A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

公开(公告)号：US11113210B2

公开(公告)日：2021-09-07

申请号：US16574386

申请日：2019-09-18

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Wongyu Shin ,  Leesup Kim ,  Youngsuk Moon ,  Yongkee Kwon ,  Jaemin Jang

IPC: G06F13/16 ,  G06F12/02 ,  G06F3/06 ,  G06F13/36 ,  G06F12/06

Abstract: A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.