知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.016 seconds)

    SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF
    2.
    发明申请
    SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20140175537A1

    公开(公告)日：2014-06-26

    申请号：US13845693

    申请日：2013-03-18

    Applicant: SK HYNIX INC.

    Inventor： Min Yong LEE ,  Jin Ku LEE ,  Jong Chul LEE

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L27/1203 ,  H01L21/26533 ,  H01L21/84

    Abstract: The semiconductor apparatus includes a semiconductor substrate, an insulating layer formed in the semiconductor substrate to be spaced from a surface of the semiconductor substrate by a predetermined depth and formed to extend to a first direction to have a predetermined width, and an active region formed to be in contact with the semiconductor substrate below the insulating layer through a source post that is formed to vertically penetrate a predetermined portion of the insulating layer, and formed on the insulating layer and the source post to extend to the first direction to have a predetermined width.

    Abstract translation: 半导体装置包括：半导体衬底;形成在半导体衬底中的绝缘层，以与半导体衬底的表面间隔预定深度并形成为延伸到具有预定宽度的第一方向;以及有源区形成为 通过形成为垂直穿过绝缘层的预定部分的源极与绝缘层下方的半导体衬底接触，并且形成在绝缘层和源极柱上以向第一方向延伸以具有预定宽度 。

    ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
    3.
    发明申请
    ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 有权
    访问设备，其制造方法和具有该接收设备的半导体存储器件

    公开(公告)号：US20150200088A1

    公开(公告)日：2015-07-16

    申请号：US14668330

    申请日：2015-03-25

    Applicant: SK hynix Inc.

    Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

    IPC: H01L21/02

    CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

    Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

    Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。

    ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME
    7.
    发明申请
    ACCESS DEVICE, FABRICATION METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME 有权
    访问设备，其制造方法和具有该接收设备的半导体存储器件

    公开(公告)号：US20140054532A1

    公开(公告)日：2014-02-27

    申请号：US13713534

    申请日：2012-12-13

    Applicant: SK HYNIX INC.

    Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

    IPC: H01L29/36 ,  H01L21/02

    CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

    Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

    Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。

Patent Agency Ranking