公开(公告)号：US20190189691A1

公开(公告)日：2019-06-20

申请号：US16109268

申请日：2018-08-22

Applicant: SK hynix Inc.

Inventor： Hyung Suk LEE

IPC: H01L27/24 ,  H01L23/36 ,  H01L27/22

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes stack structures, a gap-fill layer filling spaces between the stack structures, and nanopores located in the gap-fill layer. Each of the stack structures includes a memory pattern. The nanopores are distributed in a portion of the gap-fill layer that is located at a level corresponding to where the memory pattern is located in each of the stack structures.

公开(公告)号：US20200066988A1

公开(公告)日：2020-02-27

申请号：US16407845

申请日：2019-05-09

Applicant: SK hynix Inc.

Inventor： Hyung Suk LEE

IPC: H01L45/00 ,  H01L27/24

Abstract: A method for fabricating an electronic device including a semiconductor memory includes forming a chalcogenide layer, forming a first conductive layer on the chalcogenide layer, and increasing a density of an interface between the chalcogenide layer and the first conductive layer by injecting or irradiating ions onto the interface.

公开(公告)号：US20150200088A1

公开(公告)日：2015-07-16

申请号：US14668330

申请日：2015-03-25

Applicant: SK hynix Inc.

Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

IPC: H01L21/02

CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。

公开(公告)号：US20140054532A1

公开(公告)日：2014-02-27

申请号：US13713534

申请日：2012-12-13

Applicant: SK HYNIX INC.

Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

IPC: H01L29/36 ,  H01L21/02

CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。