公开(公告)号：US20140179069A1

公开(公告)日：2014-06-26

申请号：US13845770

申请日：2013-03-18

Applicant: SK HYNIX INC.

Inventor： Young Ho LEE ,  Seung Beom BAEK

IPC: H01L29/66

CPC classification number: H01L21/84 ,  H01L21/7624 ,  H01L27/1203

Abstract: A method of fabricating a semiconductor apparatus includes forming an insulating layer on a semiconductor substrate, forming a source post in the insulating layer, and forming a semiconductor layer over the source post and the insulating layer.

Abstract translation: 一种制造半导体装置的方法包括在半导体衬底上形成绝缘层，在绝缘层中形成源极柱，并在源极和绝缘层上形成半导体层。

公开(公告)号：US20150200088A1

公开(公告)日：2015-07-16

申请号：US14668330

申请日：2015-03-25

Applicant: SK hynix Inc.

Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

IPC: H01L21/02

CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。

公开(公告)号：US20140322886A1

公开(公告)日：2014-10-30

申请号：US14323765

申请日：2014-07-03

Applicant: SK hynix Inc.

Inventor： Min Yong LEE ,  Young Ho LEE ,  Seung Beom BAEK ,  Jong Chul LEE

IPC: H01L45/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2481 ,  H01L29/6609 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/16

Abstract: A resistive memory device and a fabrication method thereof are provided. The resistive memory device includes a variable resistive layer formed on a semiconductor substrate in which a bottom structure is formed, a lower electrode formed on the variable resistive layer, a switching unit formed on the lower electrode, and an upper electrode formed on the switching unit.

Abstract translation: 提供了一种电阻式存储器件及其制造方法。 电阻式存储器件包括形成在其上形成底部结构的半导体衬底上的可变电阻层，形成在可变电阻层上的下电极，形成在下电极上的开关单元和形成在开关单元上的上电极 。

公开(公告)号：US20140054532A1

公开(公告)日：2014-02-27

申请号：US13713534

申请日：2012-12-13

Applicant: SK HYNIX INC.

Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

IPC: H01L29/36 ,  H01L21/02

CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。

公开(公告)号：US20130334670A1

公开(公告)日：2013-12-19

申请号：US13716011

申请日：2012-12-14

Applicant: SK HYNIX INC.

Inventor： Seung Beom BAEK ,  Su Jin CHAE ,  Min Yong LEE ,  Hye Jin SEO ,  Young Ho LEE ,  Jin Ku LEE ,  Jong Chul LEE

IPC: H01L29/868 ,  H01L21/02

CPC classification number: H01L29/868 ,  H01L21/02518 ,  H01L21/22 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66136

Abstract: A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a first type semiconductor layer doped with an N type ion, a second type semiconductor layer formed over the first type semiconductor layer, and a silicon germanium (SiGe) layer doped with a P type ion formed over the second type semiconductor layer.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括掺杂有N型离子的第一类型半导体层，在第一类型半导体层上形成的第二类型半导体层和在第二类型半导体层上形成的掺杂有P型离子的硅锗（SiGe）层 。