公开(公告)号：US20240413088A1

公开(公告)日：2024-12-12

申请号：US18813018

申请日：2024-08-23

Applicant: SK hynix Inc.

Inventor： Jin Yul LEE ,  Beom Ho MUN ,  Seung Woo JIN ,  Keum Bum LEE

IPC: H01L23/532 ,  H01L21/768 ,  H10B12/00

Abstract: Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance between neighboring conductive lines and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device comprises: a conductive line formed over a substrate; and a multi-layered spacer covering both sidewalls of the conductive line, wherein the multi-layered spacer is stacked in the order of a diffusion barrier material, boron nitride layer, and an antioxidant material.

公开(公告)号：US20140054532A1

公开(公告)日：2014-02-27

申请号：US13713534

申请日：2012-12-13

Applicant: SK HYNIX INC.

Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

IPC: H01L29/36 ,  H01L21/02

CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。

公开(公告)号：US20150200088A1

公开(公告)日：2015-07-16

申请号：US14668330

申请日：2015-03-25

Applicant: SK hynix Inc.

Inventor： Young Ho LEE ,  Keum Bum LEE ,  Min Yong LEE ,  Hyung Suk LEE ,  Seung Beom BAEK

IPC: H01L21/02

CPC classification number: H01L21/0257 ,  H01L21/02373 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/2205 ,  H01L27/2409 ,  H01L29/161 ,  H01L29/36 ,  H01L29/66121 ,  H01L29/868

Abstract: An access device having a reduced height and capable of suppressing leakage current, a method of fabricating the same, and a semiconductor memory device including the same, are provided. The access device may include a stacked structure including a first-type semiconductor layer having a first dopant, a second-type semiconductor layer having a second dopant, and a third-type semiconductor layer. A first counter-doping layer, having a counter-dopant to the first dopant, is interposed between the first-type semiconductor layer and the third-type semiconductor layer. A second counter-doping layer, having a counter-dopant to the second dopant, is interposed between the third-type semiconductor layer and the second-type semiconductor layer.

Abstract translation: 提供具有减小的高度并且能够抑制泄漏电流的访问装置，其制造方法以及包括该访问装置的半导体存储装置。 存取装置可以包括堆叠结构，其包括具有第一掺杂剂的第一类型半导体层，具有第二掺杂剂的第二类型半导体层和第三类型半导体层。 具有与第一掺杂剂相反的掺杂剂的第一相掺杂层介于第一型半导体层和第三型半导体层之间。 具有与第二掺杂剂相反的掺杂剂的第二反掺杂层插入在第三类型半导体层和第二类型半导体层之间。