公开(公告)号：US20170170831A1

公开(公告)日：2017-06-15

申请号：US15086669

申请日：2016-03-31

申请人： SK hynix Inc.

发明人： Jung Ho LIM ,  Jung Hwan JI

IPC分类号： H03K19/003 ,  H03K5/06 ,  H03K19/20

CPC分类号： H03K19/00384 ,  H03K5/06 ,  H03K19/20

摘要： An inverter circuit includes a pull-up control circuit and a pull-up drive circuit. The pull-up control circuit generates a drive signal which is enabled during a first time period in response to an input signal and an output signal. The pull-up drive circuit drives the output signal to a power supply voltage in response to the input signal and the drive signal. The pull-up drive unit drives the output signal with a first drivability during the first time period and drives the output signal with a second drivability during a second time period.

公开(公告)号：US20230273860A1

公开(公告)日：2023-08-31

申请号：US17882123

申请日：2022-08-05

申请人： SK hynix Inc.

发明人： Seon Woo HWANG ,  Seong Jin KIM ,  Jung Hwan JI

IPC分类号： G06F11/10

CPC分类号： G06F11/108

摘要： The present technology may include an error correction code engine configured to generate a parity bit and syndrome information by performing an operation according to operation source data, and a data processing circuit configured to simultaneously output the parity bit and first delay data, which is generated by delaying input data by a first time according to a write operation, simultaneously output the syndrome information and second delay data, which is generated by delaying input data by a second time according to a read operation, and to share substantially the same signal path in generating the first delay data and in generating the second delay data.

公开(公告)号：US20240321383A1

公开(公告)日：2024-09-26

申请号：US18678663

申请日：2024-05-30

申请人： SK hynix Inc.

发明人： Seon Woo HWANG ,  Seong Jin KIM ,  Jung Hwan JI

IPC分类号： G11C29/52 ,  G11C7/10

CPC分类号： G11C29/52 ,  G11C7/1093 ,  G11C7/1096

摘要： A semiconductor apparatus includes a parity operation circuit, a write latch circuit, a data processing circuit and a write path. The parity operation circuit generates a parity signal by performing an operation on operation source data. The write latch circuit generates a write parity signal by latching the parity signal according to a delayed write signal. The data processing circuit outputs write data as the operation source data in a write operation, and delays the operation source data by a time required for operation of the parity signal and outputs it as delayed data. The write path writes the delay data and the write parity signal to a memory area in the write operation.

公开(公告)号：US20190198110A1

公开(公告)日：2019-06-27

申请号：US16041559

申请日：2018-07-20

申请人： SK hynix Inc.

发明人： Jung Hwan JI ,  Sang Ho LEE ,  Ho Don JUNG ,  Jun Hyun CHUN

IPC分类号： G11C16/08 ,  G11C8/10 ,  G11C8/12 ,  G11C7/18 ,  G11C11/408

CPC分类号： G11C16/08 ,  G11C5/025 ,  G11C7/08 ,  G11C7/18 ,  G11C8/10 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/005

摘要： A semiconductor apparatus may include a unit memory region, a first column main decoder, a second column main decoder, and a control circuit. The unit memory region may include a plurality of sub-memory regions. The first and second column main decoders may be configured to receive and decode a column pre-decoding signal and configured to generate a respective column select signal for controlling a column access of a respective first and second half of the plurality of sub-memory regions. The control circuit may be configured to provide the column pre-decoding signal to the first or second column main decoders based on their proximities to a sub-memory region to be enabled among the plurality of sub-memory regions.

公开(公告)号：US20140176209A1

公开(公告)日：2014-06-26

申请号：US13845586

申请日：2013-03-18

申请人： SK HYNIX INC.

发明人： Jung Hwan JI ,  Geun Il LEE

IPC分类号： H03L7/099

CPC分类号： G06F1/08

摘要： A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes.

摘要翻译： 时钟发生电路包括计数代码生成单元，被配置为当使能信号有效时产生与输入时钟的频率相对应的计数代码; 控制代码生成单元，被配置为对计数代码进行解码并生成控制代码; 以及循环可变振荡单元，其被配置为响应于所述控制代码来确定输出时钟的频率。

公开(公告)号：US20240022261A1

公开(公告)日：2024-01-18

申请号：US18085236

申请日：2022-12-20

申请人： SK hynix Inc.

发明人： Seon Woo HWANG ,  Seong Jin KIM ,  Jung Hwan JI

IPC分类号： H03M13/11 ,  H03M13/00

CPC分类号： H03M13/1111 ,  H03M13/6356

摘要： In an embodiment, an error correction code circuit is provided. The error correction code circuit includes an error correction code engine and data processing circuit. The error correction code engine is configured to generate a second parity signal and syndrome information by performing an operation on operation source data and a first parity signal. The data processing circuit is configured to output write data as the operation source data and output an internally generated dummy parity signal as the first parity signal during a write operation, and to output read data as the operation source data and output a read parity signal as the first parity signal during a read operation.

公开(公告)号：US20230215508A1

公开(公告)日：2023-07-06

申请号：US17737268

申请日：2022-05-05

申请人： SK hynix Inc.

发明人： Seon Woo HWANG ,  Seong Jin KIM ,  Jung Hwan JI

IPC分类号： G11C29/42 ,  G11C29/12 ,  G11C29/46 ,  G11C7/10 ,  G11C7/06

CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/46 ,  G11C7/1096 ,  G11C7/1069 ,  G11C7/065

摘要： The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.

公开(公告)号：US20160260470A1

公开(公告)日：2016-09-08

申请号：US14717072

申请日：2015-05-20

申请人： SK hynix Inc.

发明人： Jung Hwan JI ,  Geun Il LEE

IPC分类号： G11C11/4096 ,  G11C11/408 ,  G11C11/4074 ,  G11C11/406

CPC分类号： G11C11/4096 ,  G11C11/40603 ,  G11C11/40611 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A semiconductor system may include a first semiconductor configured to output a command signal and an address signal. The semiconductor system may include a second semiconductor device configured to include a first operation circuit including a first MOS transistor and a second operation circuit including a second MOS transistor. The first MOS transistor and the second MOS transistor may be turned on in response to a first internal command signal when a first operation is executed according to the command signal. The first MOS transistor may be turned on in response to a period signal generated from the address signal when a second operation is executed according to the command signal.

摘要翻译： 半导体系统可以包括被配置为输出命令信号和地址信号的第一半导体。 半导体系统可以包括第二半导体器件，其被配置为包括包括第一MOS晶体管的第一操作电路和包括第二MOS晶体管的第二操作电路。 当根据命令信号执行第一操作时，第一MOS晶体管和第二MOS晶体管可以响应于第一内部命令信号而导通。 当根据命令信号执行第二操作时，第一MOS晶体管可以响应于从地址信号产生的周期信号而导通。