公开(公告)号：US11501808B2

公开(公告)日：2022-11-15

申请号：US16888492

申请日：2020-05-29

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Ie Ryung Park ,  Dong Sop Lee ,  Sung Yeob Cho

IPC分类号： G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  H03L7/081 ,  H03L7/089

摘要： A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

公开(公告)号：US12026400B2

公开(公告)日：2024-07-02

申请号：US17824803

申请日：2022-05-25

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Ie Ryung Park ,  Dong Sop Lee ,  Sung Yeob Cho

IPC分类号： G06F3/06 ,  G11C16/04 ,  G11C11/56

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/0483 ,  G11C11/5621 ,  G11C11/5671

摘要： A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

公开(公告)号：US11803334B2

公开(公告)日：2023-10-31

申请号：US17824779

申请日：2022-05-25

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Ie Ryung Park ,  Dong Sop Lee ,  Sung Yeob Cho

IPC分类号： G06F3/06 ,  G11C16/04 ,  G11C11/56

CPC分类号： G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G11C16/0483 ,  G11C11/5621 ,  G11C11/5671

摘要： A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

公开(公告)号：US11646068B2

公开(公告)日：2023-05-09

申请号：US17477358

申请日：2021-09-16

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Ie Ryung Park ,  Dong Sop Lee ,  Sung Yeob Cho

IPC分类号： G11C8/00 ,  G11C7/22 ,  G11C7/10 ,  H03L7/081 ,  H03L7/089

CPC分类号： G11C7/222 ,  G11C7/1051 ,  G11C7/1072 ,  H03L7/089 ,  H03L7/0814

摘要： A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

公开(公告)号：US11581055B2

公开(公告)日：2023-02-14

申请号：US17393288

申请日：2021-08-03

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Ie Ryung Park

IPC分类号： G11C29/12 ,  G11C29/42 ,  G11C29/36

摘要： A memory system includes a memory device and a controller. The controller is coupled to the memory device through input/output (I/O) lines. The controller includes an interface component and a dummy power consumption component. The interface component performs a signal training operation for adjusting a timing of a clock signal, to which test data is synchronized. The dummy power consumption component performs a dummy power consumption operation while the signal training operation is performed.

公开(公告)号：US11355213B2

公开(公告)日：2022-06-07

申请号：US16868116

申请日：2020-05-06

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Ie Ryung Park

IPC分类号： G11C29/38 ,  G06F1/06 ,  G11C29/12 ,  G11C7/22

摘要： A memory system including: a memory device looping back a first clock to generate a second clock and outputting read data that are read from a memory cell region of the memory device in synchronization with the second clock; and a memory controller generating the first clock that includes a plurality of modulation sections by performing a modulation operation on a source clock according to a specific scheme, outputting the first clock to the memory device, and receiving the read data in response to the second clock. The read data includes a plurality of section data corresponding to the plurality of modulation sections included in the second clock, respectively, and the memory controller verifies reliability of each of the plurality of section data included in the read data by performing a demodulation operation on the second clock according to the specific scheme.

公开(公告)号：US11676643B2

公开(公告)日：2023-06-13

申请号：US17307362

申请日：2021-05-04

申请人： SK hynix Inc.

发明人： Ie Ryung Park ,  Hyun Sub Kim ,  Dong Sop Lee

IPC分类号： G11C7/10 ,  G11C5/14 ,  G11C7/22

CPC分类号： G11C7/1039 ,  G11C5/14 ,  G11C7/1045 ,  G11C7/1063 ,  G11C7/222

摘要： The present technology relates to an electronic device. More specifically, the present technology relates to a memory device, a storage device, and a method of operating a memory controller. According to an embodiment, a memory device that outputs read data in response to a read enable signal provided from a memory controller includes a plurality of memory cells configured to store data, a plurality of page buffers configured to sense the data stored in the plurality of memory cells through a plurality of bit lines, and a data output controller configured to select a target page buffer to output data from among the plurality of page buffers according to a page buffer address control signal provided from the memory controller and control the selected target page buffer to output data stored in the selected target page buffer according to the read enable signal, while the read enable signal is input.

公开(公告)号：US11507310B2

公开(公告)日：2022-11-22

申请号：US16888444

申请日：2020-05-29

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Ie Ryung Park ,  Dong Sop Lee ,  Sung Yeob Cho

IPC分类号： G11C29/56 ,  G11C29/40 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56

摘要： A memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. A memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.

公开(公告)号：US09082642B2

公开(公告)日：2015-07-14

申请号：US14043908

申请日：2013-10-02

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Jung Won Park

IPC分类号： G11C16/04 ,  G11C16/12 ,  H01L27/105 ,  H01L27/088 ,  G11C8/08 ,  H01L27/02 ,  H01L27/115

CPC分类号： H01L27/088 ,  G11C8/08 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  H01L27/0207 ,  H01L27/11526

摘要： Disclosed is a semiconductor device, including: an active region defined in a shape extended in at least four different directions in a semiconductor substrate; and gates of first to fourth transistors formed on extended portions of the active region, respectively, in which the first to fourth transistors share one junction area.

摘要翻译： 公开了一种半导体器件，包括：在半导体衬底中以至少四个不同方向延伸的形状限定的有源区; 以及分别形成在有源区域的延伸部分上的第一至第四晶体管的栅极，其中第一至第四晶体管共享一个接合区域。

公开(公告)号：US11600311B2

公开(公告)日：2023-03-07

申请号：US17368652

申请日：2021-07-06

申请人： SK hynix Inc.

发明人： Hyun Sub Kim ,  Ie Ryung Park ,  Dong Sop Lee

IPC分类号： G11C7/22 ,  G11C7/10 ,  G06F1/12 ,  G06F1/08 ,  G06F13/16

摘要： A memory controller may control a memory device. The memory device may be coupled to the memory controller through a channel. The memory controller may include an idle time monitor and a clock signal generator. The idle time monitor may output an idle time interval of the memory device. The idle time interval may be between an end time of a previous operation of the memory device and a start time of a current operation. The clock signal generator may generate a clock signal based on the idle time interval and output the clock signal to the memory device through the channel to perform a current operation.