公开(公告)号：US08970050B2

公开(公告)日：2015-03-03

申请号：US13728549

申请日：2012-12-27

Applicant: SK Hynix Inc.

Inventor： Chang Hyun Lee

IPC: H01L29/40 ,  H01L21/44 ,  H01L23/498 ,  H01L21/768 ,  H01L23/544 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/768 ,  H01L23/481 ,  H01L23/544 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54473 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device includes a first chip and a second chip connected to the first chip physically and electrically, wherein the first chip and the second chip are coupled by through silicon vias (TSVs) formed in a first region, and the first chip and the second chip are coupled by alignment keys formed in second regions.

Abstract translation: 半导体存储器件包括物理和电连接到第一芯片的第一芯片和第二芯片，其中第一芯片和第二芯片通过形成在第一区域中的硅通孔（TSV）耦合，并且第一芯片和 第二芯片通过形成在第二区域中的对准键耦合。

公开(公告)号：US09261557B1

公开(公告)日：2016-02-16

申请号：US14532725

申请日：2014-11-04

Applicant: SK hynix Inc.

Inventor： Chang Hyun Lee ,  Young Jun Ku

IPC: G11C29/00 ,  G01R31/317 ,  G11C7/10 ,  G11C7/22 ,  G11C29/02

CPC classification number: G01R31/31727 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/40

Abstract: A semiconductor apparatus includes a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable signal; a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test enable signal; an input/output buffer unit configured to receive input patterns and generate output patterns; and a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable signal.

Abstract translation: 半导体装置包括：时钟使能信号缓冲器单元，被配置为接收输入时钟使能信号，并产生输出时钟使能信号; 缓冲器控制单元，被配置为响应于所述输出时钟使能信号和测试使能信号产生缓冲器使能信号; 配置为接收输入图案并生成输出图案的输入/输出缓冲器单元; 以及压缩测试单元，被配置为根据测试使能信号测试输出模式和输出时钟使能信号。

公开(公告)号：US11755045B1

公开(公告)日：2023-09-12

申请号：US17882256

申请日：2022-08-05

Applicant: SK hynix Inc.

Inventor： Jin Hoon Hyun ,  Chang Hyun Lee

IPC: G05F1/46 ,  G05F1/595

CPC classification number: G05F1/465 ,  G05F1/595

Abstract: An internal voltage generation circuit includes a shifting source voltage generation circuit configured to generate a shifting source voltage having a voltage level that falls as a voltage level of a power supply voltage rises during a period when the power supply voltage is lower than a preset voltage level. The internal voltage generation circuit also includes an internal voltage regulator configured to generate a driving signal through a level shifting operation that is performed according to the shifting source voltage received when driving an internal voltage and configured to drive the internal voltage based on the driving signal.

公开(公告)号：US09947374B2

公开(公告)日：2018-04-17

申请号：US15080216

申请日：2016-03-24

Applicant: SK hynix Inc.

Inventor： Chang Hyun Lee

IPC: G05F1/10 ,  G11C5/14 ,  G11C7/10 ,  G11C16/26

CPC classification number: G11C5/147 ,  G11C5/143 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/26

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a power supply voltage and first data. The second semiconductor device generates a control voltage whose level is adjusted in response to the power supply voltage. The second semiconductor device also receives the first data to generate second data having a swing width different from a swing width of the first data. The second data being driven is controlled by the control voltage.

公开(公告)号：US10049763B2

公开(公告)日：2018-08-14

申请号：US15146503

申请日：2016-05-04

Applicant: SK hynix Inc.

Inventor： Chang Hyun Lee ,  Young Jun Ku

IPC: G01R31/3181 ,  G11C29/08 ,  G11C29/12 ,  G11C29/26 ,  G11C29/46 ,  G11C29/50 ,  G11C29/56

Abstract: A semiconductor memory apparatus includes a plurality of stacked semiconductor dies including a first semiconductor die comprising a first internal circuit configured to control input timing of a test control signal that is output as a plurality of delayed test control signals to the plurality of stacked semiconductor dies according to the controlled input timing in response to a test mode signal.

公开(公告)号：US09349488B2

公开(公告)日：2016-05-24

申请号：US14495988

申请日：2014-09-25

Applicant: SK hynix Inc.

Inventor： Chang Hyun Lee ,  Young Jun Ku

IPC: G11C29/56 ,  G11C29/02 ,  G11C29/50 ,  G11C29/12

CPC classification number: G11C29/12015 ,  G11C29/023 ,  G11C29/08 ,  G11C29/12 ,  G11C29/26 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/2602 ,  G11C2029/5602

Abstract: A semiconductor memory apparatus includes a plurality of data storage regions; a first internal circuit configured to input a plurality of control signals to the plurality of data storage regions; and a second internal circuit configured to control input timing of a test control signal, and input the test control signal to the plurality of data storage regions according to the controlled input timing in response to a test mode signal.

Abstract translation: 半导体存储装置包括多个数据存储区域; 第一内部电路，被配置为将多个控制信号输入到所述多个数据存储区域; 以及第二内部电路，被配置为控制测试控制信号的输入定时，并且响应于测试模式信号，根据受控的输入定时将测试控制信号输入到多个数据存储区域。