-
公开(公告)号：US11361816B2
公开(公告)日：2022-06-14
申请号：US16996412
申请日：2020-08-18
IPC分类号： G11C11/4094 , G11C11/4093 , G11C5/02 , G11C11/408 , G11C11/4074
摘要： Apparatuses and techniques are described for providing separate source regions in the substrate below a block of memory cells. The source regions can be separately driven by respective voltage drivers to provide benefits such as more uniform program and erase speeds and narrower threshold voltage distributions. In one approach, a single source region is provided and divided into multiple source regions by etching trenches and filling the trenches with an insulating material. Contacts to the source regions can include post-shaped contacts which extend through the block for each source region. In another approach, one or more planar contacts extend through the block for each source region. In another aspect, a program operation applies different voltages to the respective source regions during a verify test of a program operation.
-
公开(公告)号：US11355437B2
公开(公告)日：2022-06-07
申请号：US16984700
申请日：2020-08-04
发明人： Zhixin Cui , Yukihiro Sakotsubo
IPC分类号： H01L27/11 , H01L23/535 , H01L27/11582 , H01L23/522 , H01L21/768 , H01L25/065 , H01L25/18 , H01L23/00 , H01L25/00 , H01L27/11556
摘要： A semiconductor die can include an alternating stack of insulating layers and electrically conductive layers located on a substrate, memory stack structures extending through the alternating stack, drain regions located at a first end of a respective one of the vertical semiconductor channels of a memory stack structure, and bit lines extending over the drain regions and electrically connected to a respective subset of the drain regions. At least of a subset of the bit lines includes bump-containing bit lines. Each of the bump-containing bit lines includes a line portion and a bump portion that protrudes upward from a top surface of the line portion by a bump height. Bit line contact via structures overlie the bit lines and contact a bump portion of a respective one of the bump-containing bit lines.
-
公开(公告)号：US11244958B2
公开(公告)日：2022-02-08
申请号：US16888014
申请日：2020-05-29
发明人： Zhixin Cui , Fei Zhou , Raghuveer S. Makala
IPC分类号： H01L27/11582 , H01L21/3105 , H01L27/1157 , H01L27/11524 , H01L23/528 , H01L23/532 , H01L29/08 , H01L23/522 , H01L21/02 , H01L21/768 , H01L21/3213 , H01L21/311 , H01L27/11556
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
-
公开(公告)号：US11222954B2
公开(公告)日：2022-01-11
申请号：US16828129
申请日：2020-03-24
IPC分类号： G11C11/34 , H01L29/423 , H01L27/11582 , H01L29/417 , H01L21/28 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/04 , H01L27/11565
摘要： A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.
-
公开(公告)号：US10930674B2
公开(公告)日：2021-02-23
申请号：US16878865
申请日：2020-05-20
发明人： Zhixin Cui , Masatoshi Nishikawa , Yanli Zhang
IPC分类号： H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L21/764 , H01L27/1157 , H01L29/06 , H01L21/822 , H01L21/8234 , H01L21/8239 , H01L29/66 , H01L21/28 , H01L27/11578 , H01L27/11575 , H01L27/11519 , H01L27/11529
摘要： A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.
-
6.发明申请公开(公告)号：US20210066347A1
公开(公告)日：2021-03-04
申请号：US17098743
申请日：2020-11-16
发明人： Monica Titus , Zhixin Cui , Senaka Kanakamedala , Yao-Sheng Lee , Chih-Yu Lee
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/11575
摘要： A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.
-
公开(公告)号：US10903230B2
公开(公告)日：2021-01-26
申请号：US16181721
申请日：2018-11-06
发明人： Michimoto Kaminaga , Zhixin Cui
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11565 , H01L21/768 , H01L27/11556 , H01L23/532 , H01L23/522 , H01L27/11575 , H01L27/11519 , H01L27/11524 , H01L27/11526
摘要： A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-insulated structure includes a conductive via structure having an upper conductive via portion overlying and contacting an annular area of a top surface of one of the electrically conductive layers, a lower conductive via portion having a lesser lateral dimension than the upper conductive via portion and extending through at least a bottommost one of the electrically conductive layers, and an interconnection conductive via portion located between the upper conductive via portion and the lower conductive via portion and contacting a cylindrical sidewall of the one of the electrically conductive layers.
-
8.发明申请公开(公告)号：US20200312875A1
公开(公告)日：2020-10-01
申请号：US16888014
申请日：2020-05-29
发明人： Zhixin Cui , Fei Zhou , Raghuveer S. Makala
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11524 , H01L23/532 , H01L21/3213 , H01L21/02 , H01L21/768 , H01L29/08 , H01L27/11556 , H01L21/3105 , H01L23/528 , H01L21/311 , H01L23/522
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
-
9.发明申请公开(公告)号：US20200312706A1
公开(公告)日：2020-10-01
申请号：US16362895
申请日：2019-03-25
发明人： Zhixin Cui , Fei Zhou , Raghuveer S. Makala
IPC分类号： H01L21/768 , H01L27/11556 , H01L27/11582 , H01L23/532 , H01L23/522
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
-
公开(公告)号：US10777575B1
公开(公告)日：2020-09-15
申请号：US16361722
申请日：2019-03-22
发明人： Zhixin Cui , Kiyohiko Sakakibara , Yanli Zhang
IPC分类号： H01L27/11582 , H01L27/11573 , H01L27/1157 , H01L27/11565 , H01L27/11575
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.
-
-
-
-
-
-
-
-
-
搜索结果
55 条记录 (耗时 0.02 秒)
