公开(公告)号：US20180130786A1

公开(公告)日：2018-05-10

申请号：US15635615

申请日：2017-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SHARMA DEEPAK ,  RAJEEV RANJAN ,  KUCHANURI SUBHASH ,  CHULHONG PARK ,  JAESEOK YANG ,  KWANYOUNG CHUN

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/423 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L21/823475 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a first active pattern extending in a first direction on a first region and a second region of a substrate, a first dummy gate electrode extending in a second direction crossing the first active pattern between the first region and the second region, a contact structure contacting the first dummy gate electrode and extending in the first direction, and a power line disposed on the contact structure and electrically connected to the contact structure. The power line extends in the first direction. The contact structure overlaps with the power line when viewed in a plan view.

公开(公告)号：US20200144129A1

公开(公告)日：2020-05-07

申请号：US16439860

申请日：2019-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAESEOK YANG ,  HAEWANG LEE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/308

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

公开(公告)号：US20210057284A1

公开(公告)日：2021-02-25

申请号：US17089822

申请日：2020-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG-HUN KIM ,  JAESEOK YANG ,  HAEWANG LEE

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L27/088

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.

公开(公告)号：US20170154976A1

公开(公告)日：2017-06-01

申请号：US15244265

申请日：2016-08-23

Applicant: SAMSUNG ELECTRONICS CO. LTD.

Inventor： IN-WOOK OH ,  HYUNJAE LEE ,  JAESEOK YANG

IPC: H01L29/66

CPC classification number: H01L29/6681 ,  H01L21/76816 ,  H01L21/823821 ,  H01L21/845 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/3223

Abstract: A method of fabricating a semiconductor device includes providing a substrate that includes first and second main regions and a dummy region, and forming dummy active patterns on the dummy region. The first and second main regions are spaced apart from each other in a first direction and the dummy region includes a dummy connection region between the first and second main regions and first and second dummy cell regions spaced apart from each other in a second direction. First dummy active patterns, second dummy active patterns, and connection dummy active patterns connecting some of the first dummy active patterns to some of the second dummy active patterns are provided on the first and second dummy cell regions and the dummy connection region, respectively.