公开(公告)号：US20140203362A1

公开(公告)日：2014-07-24

申请号：US13783513

申请日：2013-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon-Hae KIM ,  Jong-Shik YOON ,  Young-Gun KO

IPC: H01L29/786

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: Semiconductor devices are provided. The semiconductor devices may include an active pattern and a insulation layer. The semiconductor devices may include a gate that is on the active pattern and that includes a first material, and a dummy gate that is on the insulation layer and that includes a second material different from the first material.

Abstract translation: 提供半导体器件。 半导体器件可以包括有源图案和绝缘层。 半导体器件可以包括位于有源图案上的并且包括第一材料的栅极和位于绝缘层上并且包括不同于第一材料的第二材料的伪栅极。

公开(公告)号：US20180254188A1

公开(公告)日：2018-09-06

申请号：US15969137

申请日：2018-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae KIM ,  Hwa-sung RHEE ,  Keun-hwi CHO

IPC: H01L21/285 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L21/28518 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a gate structure extending in a second direction on a substrate, a source/drain layer disposed on a portion of the substrate adjacent the gate structure in a first direction crossing the second direction, a first conductive contact plug on the gate structure, and a second contact plug structure disposed on the source/drain layer. The second contact plug structure includes a second conductive contact plug and an insulation pattern, and the second conductive contact plug and the insulation pattern are disposed in the second direction and contact each other. The first conductive contact plug and the insulation pattern are adjacent to each other in the first direction. The first and second conductive contact plugs are spaced apart from each other.

公开(公告)号：US20150061073A1

公开(公告)日：2015-03-05

申请号：US14245079

申请日：2014-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Hae KIM ,  Hwa-Sung RHEE

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L27/016 ,  H01L21/76879 ,  H01L23/5223 ,  H01L23/5228 ,  H01L27/10852 ,  H01L27/10858 ,  H01L27/10861 ,  H01L28/20 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, the interlayer dielectric layer having an upper surface, a lower plug extending down into the interlayer dielectric layer from the upper surface of the interlayer dielectric layer, the lower plug having an upper surface, a first dielectric layer pattern on the upper surface of the lower plug, at least a portion of the first dielectric layer pattern being directly connected to the upper surface of the lower plug, a first metal electrode pattern on the first dielectric layer pattern, a first upper plug electrically connected to the first metal electrode pattern, and a second upper plug on the lower plug, the second upper plug being spaced apart from the first upper plug.

Abstract translation: 半导体器件包括在衬底上的层间电介质层，层间绝缘层具有上表面，下电极从层间电介质层的上表面向下延伸到层间电介质层中，下插塞具有上表面， 第一电介质层图案在下塞子的上表面上，第一介电层图案的至少一部分直接连接到下塞子的上表面，第一介电层图案上的第一金属电极图案，第一上层 电插头与第一金属电极图形电连接，第二上插头位于下插头上，第二上插头与第一上插头间隔开。

公开(公告)号：US20130248950A1

公开(公告)日：2013-09-26

申请号：US13692012

申请日：2012-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong-Seong KANG ,  Yoon-Hae KIM ,  Jong-Shik YOON

IPC: H01L29/78 ,  H01L29/40

CPC classification number: H01L29/78 ,  H01L21/7682 ,  H01L21/76897 ,  H01L21/823456 ,  H01L21/823468 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/4991 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656

Abstract: Semiconductor devices, and a method of manufacturing the same, include a gate insulating film pattern over a semiconductor substrate. A gate electrode is formed over the gate insulating film pattern. A spacer structure is formed on at least one side of the gate electrode and the gate insulating film pattern. The spacer structure includes a first insulating film spacer contacting the gate insulating film pattern, and a second insulating film spacer on an outer side of the first insulating film spacer. The semiconductor device has an air gap between the first insulating film spacer and the second insulating film spacer.

Abstract translation: 半导体器件及其制造方法包括在半导体衬底上的栅极绝缘膜图案。 在栅极绝缘膜图案上形成栅电极。 在栅电极和栅绝缘膜图案的至少一侧上形成间隔结构。 间隔结构包括与栅极绝缘膜图案接触的第一绝缘膜间隔件和在第一绝缘膜间隔件的外侧上的第二绝缘膜间隔件。 半导体器件在第一绝缘膜间隔件和第二绝缘膜间隔件之间具有气隙。

公开(公告)号：US20130161722A1

公开(公告)日：2013-06-27

申请号：US13712109

申请日：2012-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Ho SON ,  Yoon-Hae KIM ,  Hong-Seong KANG ,  Yoon-Seok LEE ,  Junjie XIONG

IPC: H01L29/78 ,  H01L29/788

CPC classification number: H01L29/78 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/788

Abstract: A semiconductor device may include a gate structure on a substrate, the gate structure including a first metal; an insulating interlayer covering the gate structure on the substrate; a resistance pattern in the insulating interlayer, the resistance pattern having a top surface lower than a top surface of the insulating interlayer and including a second metal different from the first metal at least at an upper portion thereof; and/or a first contact plug through a first portion of the insulating interlayer, the first contact plug making direct contact with the upper portion of the resistance pattern.

Abstract translation: 半导体器件可以包括在衬底上的栅极结构，栅极结构包括第一金属; 覆盖基板上的栅极结构的绝缘夹层; 绝缘中间层中的电阻图案，电阻图案具有比绝缘中间层的顶表面低的顶表面，并且至少在其上部包括不同于第一金属的第二金属; 和/或通过绝缘中间层的第一部分的第一接触插塞，第一接触插塞与电阻图案的上部直接接触。