公开(公告)号：US10157883B2

公开(公告)日：2018-12-18

申请号：US15404090

申请日：2017-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul Park ,  Kilsoo Kim ,  In Lee

IPC: H01L25/065 ,  H01L23/00

Abstract: A semiconductor package comprises a package substrate; a first chip stack and a second chip stack mounted side by side on the package substrate, wherein the first and second chip stacks each include a plurality of semiconductor chips stacked on the package substrate, wherein each of the semiconductor chips includes a plurality of bonding pads provided on a respective edge region thereof, wherein at least some of the plurality of bonding pads are functional pads, and wherein the functional pads occupy a region that is substantially less than an entirety of the respective edge region.

公开(公告)号：US10978432B2

公开(公告)日：2021-04-13

申请号：US16419782

申请日：2019-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilsoo Kim

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L21/78

Abstract: A semiconductor package includes a first semiconductor package, a second semiconductor package on the first semiconductor package, and a plurality of connection terminals between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a package substrate, a semiconductor chip on the package substrate and having a first surface and a second surface facing each other, the first surface being adjacent to the second semiconductor package, a plurality of connection pads between the first surface of the semiconductor chip and the connection terminals, and a molding layer on the package substrate and covering side surfaces of the semiconductor chip, the molding layer being spaced apart from the connection terminals.

公开(公告)号：US08803311B2

公开(公告)日：2014-08-12

申请号：US13836937

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： In Lee ,  Kilsoo Kim

IPC: H01L23/12

CPC classification number: H05K1/0298 ,  H01L23/49816 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/4608 ,  H05K2201/10416 ,  H01L2924/00

Abstract: A wiring board and a semiconductor package are provided. The wiring board includes: a metal core including a first surface and a second surface opposite the first surface; a first buildup portion and a second buildup portion including an insulating layer and a pad pattern sequentially stacked, the first and second buildup portions being provided on the first surface and the second surface, respectively; a mask pattern including an opening exposing the pad pattern, the mask pattern being provided on the second buildup portion; and a barrier pattern in an area in which a region of the metal core which overlaps with the pad pattern of the second buildup portion is removed, wherein a minimum width of an outer circumference of the barrier pattern is greater than a maximum width of the pad pattern of the second buildup portion.

Abstract translation: 提供了布线板和半导体封装。 布线板包括：金属芯，包括第一表面和与第一表面相对的第二表面; 第一累积部分和第二累积部分，其包括依次层叠的绝缘层和焊盘图案，所述第一和第二累积部分别分别设置在所述第一表面和所述第二表面上; 掩模图案，包括露出所述焊盘图案的开口，所述掩模图案设置在所述第二堆积部分上; 以及其中去除与第二积累部分的焊盘图案重叠的金属芯的区域的区域中的阻挡图案，其中阻挡图案的外周的最小宽度大于焊盘的最大宽度 第二累积部分的图案。

公开(公告)号：US20140185389A1

公开(公告)日：2014-07-03

申请号：US14143154

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

IPC: G11C7/10

CPC classification number: G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

Abstract translation: 提供内存系统。 存储器系统可以包括多个非易失性存储器和被配置为控制多个非易失性存储器的存储器控​​制器。 此外，存储器系统可以包括连接在存储器控制器和多个非易失性存储器之间的输入/输出缓冲器电路。 数据通道可以连接在存储器控制器和输入/输出缓冲器电路之间，并且第一和第二内部数据通道可以连接在输入/输出缓冲器电路和多个非易失性存储器的相应的第一和第二组之间。 输入/输出缓冲器电路可以被配置为将数据信道连接到第一和第二内部数据信道之一。

公开(公告)号：US09899352B2

公开(公告)日：2018-02-20

申请号：US15277366

申请日：2016-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kilsoo Kim

IPC: H01L25/18 ,  H01L25/065

CPC classification number: H01L25/0652 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311

Abstract: A data storage device may include a package substrate, and an upper semiconductor chip disposed above a top surface of the package substrate. At least one lower bump is disposed on a bottom surface of the package substrate. A lower semiconductor chip is disposed on the bottom surface of the package substrate and spaced apart from the at least one lower bump. The lower semiconductor chip is thinner than the at least one lower bump.

公开(公告)号：US09263105B2

公开(公告)日：2016-02-16

申请号：US14143154

申请日：2013-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjin Jeon ,  Jeongdon Ihm ,  Kilsoo Kim ,  Jinman Han

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/04

CPC classification number: G06F3/0604 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/1096 ,  G11C7/222 ,  H01L2224/48227 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Memory systems are provided. A memory system may include a plurality of nonvolatile memories and a memory controller configured to control the plurality of nonvolatile memories. Moreover, the memory system may include an input/output buffer circuit connected between the memory controller and the plurality of nonvolatile memories. A data channel may be connected between the memory controller and the input/output buffer circuit, and first and second internal data channels may be connected between the input/output buffer circuit and respective first and second groups of the plurality of nonvolatile memories. The input/output buffer circuit may be configured to connect the data channel to one of the first and second internal data channels.

Abstract translation: 提供内存系统。 存储器系统可以包括多个非易失性存储器和被配置为控制多个非易失性存储器的存储器控​​制器。 此外，存储器系统可以包括连接在存储器控制器和多个非易失性存储器之间的输入/输出缓冲器电路。 数据通道可以连接在存储器控制器和输入/输出缓冲器电路之间，并且第一和第二内部数据通道可以连接在输入/输出缓冲器电路和多个非易失性存储器的相应的第一和第二组之间。 输入/输出缓冲器电路可以被配置为将数据信道连接到第一和第二内部数据信道之一。

公开(公告)号：US12176328B2

公开(公告)日：2024-12-24

申请号：US18447535

申请日：2023-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeho Lee ,  Kilsoo Kim

IPC: H01L25/10 ,  H01L23/538

Abstract: A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad.

公开(公告)号：US11769762B2

公开(公告)日：2023-09-26

申请号：US17160878

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeho Lee ,  Kilsoo Kim

IPC: H01L25/10 ,  H01L23/538

CPC classification number: H01L25/105 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L2225/1047

Abstract: A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad.

公开(公告)号：US10923428B2

公开(公告)日：2021-02-16

申请号：US16432551

申请日：2019-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji Hwang Kim ,  Kilsoo Kim ,  Jongbo Shim ,  Jangwoo Lee ,  Eunhee Jung

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a substrate, a semiconductor chip mounted on the substrate, an interposer chip on the semiconductor chip and including a redistribution pattern, a first pad on the interposer chip, a second pad on the interposer chip and spaced apart from the first pad, and a bonding wire electrically connected to the second pad and the first substrate. The second pad is electrically connected through the redistribution pattern to the first pad. The footprint of the interposer chip is greater than the footprint of the first semiconductor chip.

公开(公告)号：US10748871B2

公开(公告)日：2020-08-18

申请号：US16164524

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong Hwan Oh ,  Kyung Suk Oh ,  Kilsoo Kim

IPC: H01L25/065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package may include a package substrate, a first semiconductor chip on the package substrate, and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip comprises a chip substrate including a first surface and a second surface opposite to the first surface, a plurality of first chip pads between the package substrate and the chip substrate, and electrically connecting the first semiconductor chip to the package substrate, a plurality of second chip pads disposed on the second surface and between the second semiconductor chip and the second surface, and a plurality of redistribution lines on the second surface, the redistribution lines electrically connecting to the second semiconductor chip, and a plurality of bonding wires electrically connecting the redistribution lines to the package substrate.