公开(公告)号：US20160133472A1

公开(公告)日：2016-05-12

申请号：US14697258

申请日：2015-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN KIM

IPC: H01L21/28 ,  H01L29/66

CPC classification number: H01L21/28088 ,  H01L21/823821 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device includes forming an interlayer insulating layer including a first trench and a second trench on a substrate, forming a lower gate conductive layer along lateral surfaces and a bottom surface of the second trench, forming a first capping conductive layer along lateral surfaces and a bottom surface of the first trench and forming a second capping conductive layer on the lower gate conductive layer, forming a first upper gate conductive layer and a second upper gate conductive layer on the first capping conductive layer and the second capping conductive layer, respectively, forming a first barrier layer and a second barrier layer on the first upper gate conductive layer and the second upper gate conductive layer, respectively, and forming a first metal layer and a second metal layer on the first barrier layer and the second barrier layer, respectively. The first barrier layer and the second barrier layer have a thickness of 40 Å or greater.

Abstract translation: 一种制造半导体器件的方法包括：在衬底上形成包括第一沟槽和第二沟槽的层间绝缘层，沿着第二沟槽的侧表面和底表面形成下栅极导电层，沿着第一沟槽和第二沟槽形成第一覆盖导电层 横向表面和第一沟槽的底表面，并在下栅极导电层上形成第二覆盖导电层，在第一覆盖导电层和第二封盖导电层上形成第一上栅极导电层和第二上栅极导电层 分别在所述第一上栅极导电层和所述第二上栅极导电层上分别形成第一阻挡层和第二阻挡层，并且在所述第一阻挡层和所述第二阻挡层上形成第一金属层和第二金属层 层。 第一阻挡层和第二阻挡层的厚度为40埃以上。

公开(公告)号：US20140312387A1

公开(公告)日：2014-10-23

申请号：US14101381

申请日：2013-12-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN KIM

IPC: H01L29/267 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/092 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/785

Abstract: A semiconductor device includes a base layer of a group III-V compound, a channel layer disposed on the base layer and including a group IV element, a nitride layer disposed on the channel layer, a gate insulation layer disposed on the nitride layer and a gate electrode disposed on the gate insulation layer. The concentration of nitrogen atoms existing at a first interface between the nitride layer and the gate insulation layer is higher than that existing at a second interface between the nitride layer and the channel layer.

Abstract translation: 半导体器件包括III-V族化合物的基底层，设置在基底层上并包括IV族元件的沟道层，设置在沟道层上的氮化物层，设置在氮化物层上的栅极绝缘层和 栅电极设置在栅极绝缘层上。 存在于氮化物层和栅极绝缘层之间的第一界面处的氮原子的浓度高于在氮化物层和沟道层之间的第二界面处存在的氮原子的浓度。

公开(公告)号：US20170170054A1

公开(公告)日：2017-06-15

申请号：US15444567

申请日：2017-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN KIM ,  MIN-CHOUL KIM ,  BAIK-MIN SUNG ,  SANG-HYUN WOO

IPC: H01L21/762 ,  H01L27/088

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

公开(公告)号：US20160380052A1

公开(公告)日：2016-12-29

申请号：US15015937

申请日：2016-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN KIM ,  Min-Choul Kim ,  Baik-Min Sung ,  Sang-Hyun Woo

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/76232 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device includes a fin protruding from a substrate and extending in a first direction, first and second gate structures intersecting the fin, a recess formed in the fin between the first and second gate structures, a device isolation layer which fills the recess, and which has an upper surface protruded outwardly from the fin and disposed to be coplanar with upper surfaces of the first and second gate structures, a liner formed along a side walls of the device isolation layer protruded outwardly from the fin and a source/drain region disposed at both sides of the recess and spaced apart from the device isolation layer.

Abstract translation: 半导体器件包括从基板突出并沿第一方向延伸的翅片，与翅片相交的第一和第二栅极结构，形成在第一和第二栅极结构之间的翅片中的凹部，填充凹部的器件隔离层和 其具有从所述翅片向外突出并且设置成与所述第一和第二栅极结构的上表面共面的上表面，沿着从所述鳍片向外突出的所述器件隔离层的侧壁形成的衬垫和设置在所述第二栅极结构的源极/漏极区域 在凹槽的两侧并与器件隔离层隔开。

公开(公告)号：US20140227868A1

公开(公告)日：2014-08-14

申请号：US14257466

申请日：2014-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JU-YOUN KIM ,  HYUN-MIN CHOI ,  SUNG-KEE HAN ,  JE-DON KIM

IPC: H01L21/28 ,  H01L21/285

CPC classification number: H01L21/28008 ,  H01L21/28518 ,  H01L21/823462 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.