公开(公告)号：US20140106510A1

公开(公告)日：2014-04-17

申请号：US14107836

申请日：2013-12-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Eung Suek LEE ,  Jee Soo MOK ,  Jun Oh HWANG

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L21/563 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/742 ,  H01L2224/1132 ,  H01L2224/11901 ,  H01L2224/13016 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/321 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00014 ,  H01L2924/00

Abstract: In accordance with various embodiments, there is provided a method of fabricating a die mounting substrate, including the steps of preparing a mounting substrate including a pad and a die including a terminal, and printing a conductive paste bump on one of the pad or the terminal. The method further includes the step of connecting the pad and the terminal to each other using the conductive paste bump, thereby surface-mounting the die on the mounting substrate.

Abstract translation: 根据各种实施例，提供一种制造管芯安装基板的方法，包括以下步骤：制备包括焊盘和包括端子的管芯的安装基板，以及在导电焊膏或端子之一上印刷导电膏凸块 。 该方法还包括使用导电膏凸起将焊盘和端子彼此连接的步骤，从而将管芯表面安装在安装基板上。

公开(公告)号：US20170033039A1

公开(公告)日：2017-02-02

申请号：US15074376

申请日：2016-03-18

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Ki Ju LEE ,  Jun Woo MYUNG ,  No Il PARK ,  Jin Su KIM ,  Eung Suek LEE ,  Jae Hyun LIM

IPC: H01L23/498 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/4825 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2225/06524 ,  H01L2225/06572 ,  H01L2924/1531 ,  H01L2924/1532 ,  H01L2924/1533 ,  H01L2924/19106

Abstract: A semiconductor package includes a first substrate, a pattern layer disposed on the first substrate, a first chip member disposed on a surface of the first substrate, lead frames mounted on the first substrate surrounding the first chip member, and a first encapsulation layer disposed on the first substrate, encapsulating the first chip member and the lead frame, wherein upper end portions of the lead frame and the first encapsulation layer are removed, and lead frame columns are exposed through the first encapsulation layer.

Abstract translation: 半导体封装包括第一衬底，设置在第一衬底上的图案层，设置在第一衬底的表面上的第一芯片构件，安装在围绕第一芯片构件的第一衬底上的引线框架和设置在第一衬底上的第一封装层 封装第一芯片构件和引线框架的第一衬底，其中引线框架和第一封装层的上端部分被去除，并且引线框架柱通过第一封装层露出。

公开(公告)号：US20170004980A1

公开(公告)日：2017-01-05

申请号：US14987490

申请日：2016-01-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： No Il PARK ,  Seung Wook PARK ,  Eung Suek LEE ,  Tae Sung JEONG

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/67

CPC classification number: H01L21/565 ,  H01L21/566 ,  H01L21/67126 ,  H01L23/3142 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2924/1815

Abstract: An apparatus for manufacturing a semiconductor package module and a method of manufacturing a semiconductor package are provided. The apparatus for manufacturing a semiconductor package module includes a lower mold installed thereon with a board with at least one element mounted thereon, an upper mold, in a state of accommodating the board, provided above the board, a filler supplier disposed in at least one of the upper mold and the lower mold, and supplying a filler to a molding space between the board and the upper mold, and a pattern forming member provided in an inner surface of the upper mold that provides an uneven pattern on a molded part.

Abstract translation: 提供一种半导体封装模块的制造装置及半导体封装的制造方法。 用于制造半导体封装模块的装置包括安装在其上的下模，具有安装在其上的至少一个元件的板，设置在板上方的容纳板的状态的上模，设置在至少一个 并且向板和上模之间的成型空间供给填料，以及设置在上模的内表面上的图案形成构件，其在模制部件上提供不均匀图案。

公开(公告)号：US20160037619A1

公开(公告)日：2016-02-04

申请号：US14734933

申请日：2015-06-09

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Young Gwan KO ,  Jae Hoon CHOI ,  Il Jong SEO ,  Sung Uk LEE ,  Eung Suek LEE

IPC: H05K1/02 ,  H05K3/10 ,  H05K3/06 ,  H05K3/40

CPC classification number: H05K3/4682 ,  H05K3/0097 ,  H05K2203/0152 ,  H05K2203/1536

Abstract: There are provided a carrier substrate including: a first metal layer; a barrier layer formed on one surface of the first carrier metal layer; and a second metal layer formed on one surface of the barrier layer, and a method of manufacturing a printed circuit board using the same.

Abstract translation: 提供了一种载体基板，包括：第一金属层; 形成在所述第一载体金属层的一个表面上的阻挡层; 以及形成在阻挡层的一个表面上的第二金属层，以及使用其形成印刷电路板的方法。

公开(公告)号：US20160007449A1

公开(公告)日：2016-01-07

申请号：US14754363

申请日：2015-06-29

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Joon Sung KIM ,  Yong Ho BAEK ,  Jung Hyun CHO ,  Eung Suek LEE ,  Jae Hoon CHOI ,  Young Gwan KO

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/10 ,  H05K1/18 ,  H05K3/30

CPC classification number: H01L23/49827 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/5389 ,  H01L24/25 ,  H01L24/82 ,  H01L2224/04105 ,  H01L2224/19 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/83005 ,  H01L2224/92144 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/3511 ,  H05K1/0298 ,  H05K1/185 ,  H05K3/10 ,  H05K3/30 ,  H05K3/305 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2203/1469 ,  H05K2203/167

Abstract: Disclosed herein is a chip embedded substrate including: an insulating layer having outer layer circuit patterns provided on any one of an upper surface and a lower surface thereof; a chip embedded in the insulating layer; and internal circuit patterns included in the insulating layer and disposed between a height of a top surface of the chip and a height of a bottom surface thereof.

Abstract translation: 本文公开了一种芯片嵌入式基板，包括：绝缘层，其具有设置在其上表面和下表面中的任一个上的外层电路图案; 嵌入绝缘层中的芯片; 以及包括在绝缘层中并且设置在芯片的顶表面的高度和其底表面的高度之间的内部电路图案。

公开(公告)号：US20150195902A1

公开(公告)日：2015-07-09

申请号：US14592696

申请日：2015-01-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Eung Suek LEE ,  Hyo Seung NAM ,  Sung Uk LEE ,  Jae Hoon CHOI ,  II Jong SEO ,  Yong Ho BAEK

IPC: H05K1/02 ,  H05K3/00 ,  C23C14/34 ,  H05K1/09

CPC classification number: H05K3/4682 ,  H05K3/3452 ,  H05K2201/0376

Abstract: There are provided a printed circuit board and a method of manufacturing the same. The printed circuit board according to an exemplary embodiment of the present disclosure includes: an insulating layer; a first circuit buried below the insulating layer and having a lower surface formed to be exposed from a lower surface of the insulating layer; a second circuit layer formed on the insulating layer; and a first solder resist layer formed below the insulating layer and the first circuit layer and formed to expose a portion of the first circuit layer.

Abstract translation: 提供了一种印刷电路板及其制造方法。 根据本公开的示例性实施例的印刷电路板包括：绝缘层; 埋置在所述绝缘层下方并具有形成为从所述绝缘层的下表面露出的下表面的第一电路; 形成在所述绝缘层上的第二电路层; 以及形成在所述绝缘层和所述第一电路层下面并形成以暴露所述第一电路层的一部分的第一阻焊层。