公开(公告)号：US06892261B2

公开(公告)日：2005-05-10

申请号：US10774486

申请日：2004-02-10

申请人： Hiroshi Ohno ,  Tomoaki Nakamura ,  Shigenori Kaneko ,  Ryokichi Yoshizawa ,  Naoshi Kato ,  Manabu Yamauchi ,  Toshiaki Arai ,  Tomoki Sekiguchi

发明人： Hiroshi Ohno ,  Tomoaki Nakamura ,  Shigenori Kaneko ,  Ryokichi Yoshizawa ,  Naoshi Kato ,  Manabu Yamauchi ,  Toshiaki Arai ,  Tomoki Sekiguchi

IPC分类号： G06F9/455 ,  G06F9/48 ,  G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/45533 ,  G06F9/4843

摘要： An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

摘要翻译： 安装用于在单个CPU上执行的用于切换操作系统的操作系统间控制软件，并且交替地执行多个操作系统。 控制程序仅在一个操作系统上执行，该控制程序控制受控设备。 在另一个OS上执行监视控制程序和开发环境程序，并且对存储器空间进行分割，从而对控制程序的操作没有影响。 可以使用单个CPU架构来建立更高的实时性能和可靠性。

公开(公告)号：US06715016B1

公开(公告)日：2004-03-30

申请号：US09585120

申请日：2000-06-01

申请人： Hiroshi Ohno ,  Tomoaki Nakamura ,  Shigenori Kaneko ,  Ryokichi Yoshizawa ,  Naoshi Kato ,  Manabu Yamauchi ,  Toshiaki Arai ,  Tomoki Sekiguchi

发明人： Hiroshi Ohno ,  Tomoaki Nakamura ,  Shigenori Kaneko ,  Ryokichi Yoshizawa ,  Naoshi Kato ,  Manabu Yamauchi ,  Toshiaki Arai ,  Tomoki Sekiguchi

IPC分类号： G06F1324

CPC分类号： G06F9/4812 ,  G06F9/45533 ,  G06F9/4843

摘要： An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

公开(公告)号：US5787464A

公开(公告)日：1998-07-28

申请号：US794604

申请日：1997-02-03

申请人： Ryokichi Yoshizawa ,  Takeshi Miyao ,  Shigenori Kaneko ,  Tomoaki Nakamura ,  Hidebumi Miyata

发明人： Ryokichi Yoshizawa ,  Takeshi Miyao ,  Shigenori Kaneko ,  Tomoaki Nakamura ,  Hidebumi Miyata

IPC分类号： G06F11/16 ,  G06F12/00 ,  G06F12/16 ,  G06F13/40 ,  G06F13/00 ,  G06F12/06

CPC分类号： G06F13/4081

摘要： A computer system and method for enabling memory expansion without shutting off the computer system are disclosed. The computer system has a dual memory configuration and supports memory insertion and extraction while being on-line. The memory content of one system may be copied to the memory of another system according to a predetermined priority or after a predetermined delay. Memory may be used efficiently during the insertion or extraction by securing a status management table expansion area in an expanded portion of memory. Memory may be expanded in computer systems that do not have an open memory slot by replacing the installed memory with a memory having a larger capacity.

摘要翻译： 公开了一种用于在不关闭计算机系统的情况下实现存储器扩展的计算机系统和方法。 计算机系统具有双存储器配置，并且在线时支持存储器插入和提取。 一个系统的存储器内容可以根据预定的优先级或在预定的延迟之后复制到另一个系统的存储器。 在插入或提取期间，可以通过将状态管理表扩展区域固定在存储器的扩展部分中来有效地使用存储器。 通过用具有较大容量的存储器替换已安装的存储器，可以在没有打开内存插槽的计算机系统中扩展内存。

公开(公告)号：US5579508A

公开(公告)日：1996-11-26

申请号：US293334

申请日：1994-08-24

申请人： Ryokichi Yoshizawa ,  Tomoaki Nakamura ,  Shigenori Kaneko

发明人： Ryokichi Yoshizawa ,  Tomoaki Nakamura ,  Shigenori Kaneko

IPC分类号： G06F12/12 ,  G06F9/445 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F12/023

摘要： A main memory managing arrangement involves allotting a request program to one of three distinct areas of main memory by looking in an area managing table which stores head addresses and the capacities of the respective areas. The areas allocated in main memory correspond to a single OS area, a single first class program area and a single second class program area. An empty page managing table is also provided for indicating the presence or absence of an empty area conformable to a request in an allocated area. A request program is allocated to the allocated area when the presence of the empty area of required capacity is determined. The memory capacity for a resident program can be assured independently of the memory capacities for other programs to enhance reliability conformable to real-time process computers.

摘要翻译： 主存储器管理装置包括通过查找存储头部地址的区域管理表和各个区域的容量来将请求程序分配给主存储器的三个不同区域中的一个。 分配在主存储器中的区域对应于单个OS区域，单个第一类程序区域和单个第二类程序区域。 还提供了一个空页面管理表，用于指示是否存在符合分配区域中的请求的空白区域。 当确定所需容量的空区域的存在时，向所分配的区域分配请求程序。 可以独立于其他程序的存储容量来确保驻留程序的存储容量，以增强与实时处理计算机兼容的可靠性。

公开(公告)号：US06216236B1

公开(公告)日：2001-04-10

申请号：US09188903

申请日：1998-11-10

申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

IPC分类号： G06F1134

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1641 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/18 ,  G06F11/181 ,  G06F11/184 ,  G06F11/185 ,  G06F11/20 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G11C29/74

摘要： A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (220,221) may be connected in common to the processors (20-1,20-2,20-3), so that failure of one cache memory (220,221) permits the processing unit (2-1,2-2,2-n) to continue to operate using the other cache memory (220,221). Coherence of the contents of the cache memories (220,221) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (2020-1,2020-2,2020-3) of a processor (20-1,20-2,20-3) which differs from that in the external cache memory (220,221). Coherence of protocols may also ensure that data in caches (220,221) of the different processor units (2-1,2-2,2-n) are always correct.

摘要翻译： 计算机系统具有经由一个或多个系统总线（1-1,1-2）连接的多个处理单元（2-1,2-2,2-n）。 每个处理单元（2-1,2-2,2-n）在公共支撑板（PL）上具有三个或更多个处理器（20-1,20-2,20-3），并由公共时钟单元 1000）。 三个处理器（20-1,20-2,20-3）执行相同的操作，并且通过比较三个处理器（20-1,20-2,20-3）的操作来检测处理器（20-1,20-2,20-3）中的故障 （20-1,20-2,20-3）。 如果一个处理器（20-1,20-2,20-3）失败，则可以在处理单元的其他两个处理器（20-1,20-2,20-3）中继续操作（2-1,2 -2,2-n），至少暂时在更换整个处理单元（2-1,2-2,2-n）之前。 此外，处理单元（2-1,2-2,2-n）可以在时钟单元（1000）内具有多个时钟（A，B），具有切换装置，使得处理器（20-1， 20-2,20-n）通常从主时钟（A）接收时钟脉冲，但是如果主时钟（A）发生故障，则从辅助时钟（B）接收脉冲。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 另外，多个高速缓冲存储器（220,221）可以共同地连接到处理器（20-1,20-2,20-3），使得一个高速缓冲存储器（220,221）的故障允许处理单元（2-1 ，2

公开(公告)号：US5901281A

公开(公告)日：1999-05-04

申请号：US434288

申请日：1995-05-03

申请人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

发明人： Takeshi Miyao ,  Manabu Araoka ,  Tomoaki Nakamura ,  Masayuki Tanji ,  Shigenori Kaneko ,  Koji Masui ,  Saburou Iijima ,  Nobuyasu Kanekawa ,  Shinichiro Kanekawa ,  Yoshiki Kobayashi ,  Hiroaki Fukumaru ,  Katsunori Tagiri

IPC分类号： G06F11/00 ,  G06F11/14 ,  G06F11/16 ,  G06F11/18 ,  G06F11/20 ,  G11C29/00 ,  G06F11/34

CPC分类号： G06F11/187 ,  G06F11/1064 ,  G06F11/141 ,  G06F11/1604 ,  G06F11/1666 ,  G06F11/1679 ,  G06F11/181 ,  G06F11/184 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/203 ,  G06F11/2035 ,  G06F11/2043 ,  G06F12/0833 ,  G06F11/1641 ,  G06F11/18 ,  G06F11/185 ,  G06F11/20 ,  G11C29/74

摘要： A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.

摘要翻译： 计算机系统具有经由一个或多个系统总线连接的多个处理单元。 每个处理单元在公共支撑板（PL）上具有三个或更多个处理器，并由公共时钟单元控制。 三个处理器执行相同的操作，并且通过比较三个处理器的操作来检测处理器中的故障。 如果一个处理器发生故障，则在更换整个处理单元之前，至少暂时在处理单元的其他两个处理器中继续操作。 此外，处理单元可以在时钟单元内具有多个时钟（A，B），具有切换装置，使得处理器通常从主时钟（A）接收时钟脉冲，但是从辅助时钟（B ）如果主时钟（A）失败。 在主时钟和辅助时钟（A，B）之间切换涉及从时钟（A，B）的脉冲持续时间的比较。 此外，多个高速缓冲存储器可以共同地连接到处理器，使得一个高速缓冲存储器的故障允许处理单元使用另一高速缓冲存储器继续操作。 可以通过直接比较来实现高速缓冲存储器的内容的一致性，并且还可以使用比较方法来使处理器的内部高速缓冲存储器中的数据与外部高速缓冲存储器中的数据不同。 协议的一致性还可以确保不同处理器单元的高速缓存中的数据总是正确的。

公开(公告)号：US09127999B2

公开(公告)日：2015-09-08

申请号：US13332794

申请日：2011-12-21

申请人： Jiro Tsuruno ,  Tsutomu Nishiwaki ,  Tomoaki Nakamura

发明人： Jiro Tsuruno ,  Tsutomu Nishiwaki ,  Tomoaki Nakamura

IPC分类号： G01N29/00 ,  G01L1/25 ,  B25J13/08 ,  B25J19/02 ,  G01L5/22

CPC分类号： G01L1/25 ,  B25J13/083 ,  B25J19/026 ,  G01L5/228

摘要： An ultrasonic sensor includes: a substrate; an ultrasonic transducer disposed on the substrate, and configured and arranged to transmit ultrasonic waves that propagate as plane waves in a direction orthogonal to a surface of the substrate; an acoustic refracting part contacting the ultrasonic transducer, and configured and arranged to refract the ultrasonic waves transmitted from the ultrasonic transducer; an elastically deformable elastic portion contacting the acoustic refracting part; and an ultrasonic reflecting member disposed within the elastic portion, and configured and arranged to reflect the ultrasonic waves. The acoustic refracting part is configured and arranged to refract, toward the ultrasonic reflecting member, the ultrasonic waves transmitted from the ultrasonic transducer.

摘要翻译： 超声波传感器包括：基板; 超声波换能器，其设置在所述基板上，并且被构造和布置成发射在与所述基板的表面正交的方向上作为平面波传播的超声波; 与所述超声波换能器接触的声折射部，构成并配置为使从所述超声波换能器发送的超声波折射; 接触声折射部的弹性变形弹性部; 以及设置在所述弹性部内的超声波反射部件，并且被配置为被配置为反射所述超声波。 声折射部被配置并布置成朝向超声波反射部件折射从超声波换能器发送的超声波。

公开(公告)号：US08118885B2

公开(公告)日：2012-02-21

申请号：US12666894

申请日：2008-06-27

申请人： Keiichi Tateishi ,  Yoshiaki Nagata ,  Tomoaki Nakamura

发明人： Keiichi Tateishi ,  Yoshiaki Nagata ,  Tomoaki Nakamura

IPC分类号： C09B67/00 ,  C09B31/00 ,  C09D11/00

CPC分类号： C09D11/322 ,  C09B33/12

摘要： An azo pigment represented by the following general formula (1), a tautomer of the azo pigment, and a salt or a hydrate thereof: wherein each of R1, R2, P1, P2, Q1, and Q2 independently represents a hydrogen atom or a substituent, G represents the non-metallic atoms necessary to complete a 5- to 6-membered heterocyclic group, W represents a substituent capable of binding to the heterocyclic group constituted by G, t represents an integer of from 0 to 4, each of Het-1 and Het-2 independently represents a group selected from specific aromatic heterocyclic groups.

摘要翻译： 由以下通式（1）表示的偶氮颜料，偶氮颜料的互变异构体及其盐或水合物：其中R1，R2，P1，P2，Q1和Q2各自独立地表示氢原子或 G表示完成5-至6-元杂环基所必需的非金属原子，W表示能够与由G构成的杂环基结合的取代基，t表示0〜4的整数，Het -1和Het-2独立地表示选自特定芳族杂环基团的基团。

公开(公告)号：US20110030583A1

公开(公告)日：2011-02-10

申请号：US12666894

申请日：2008-06-27

申请人： Keiichi Tateishi ,  Yoshiaki Nagata ,  Tomoaki Nakamura

发明人： Keiichi Tateishi ,  Yoshiaki Nagata ,  Tomoaki Nakamura

IPC分类号： C09D11/00 ,  C09B31/02

CPC分类号： C09D11/322 ,  C09B33/12

摘要： An azo pigment represented by the following general formula (1), a tautomer of the azo pigment, and a salt or a hydrate thereof: wherein each of R1, R2, P1, P2, Q1, and Q2 independently represents a hydrogen atom or a substituent, G represents the non-metallic atoms necessary to complete a 5- to 6-membered heterocyclic group, W represents a substituent capable of binding to the heterocyclic group constituted by G, t represents an integer of from 0 to 4, each of Het-1 and Het-2 independently represents a group selected from specific aromatic heterocyclic groups.

摘要翻译： 由以下通式（1）表示的偶氮颜料，偶氮颜料的互变异构体及其盐或水合物：其中R1，R2，P1，P2，Q1和Q2各自独立地表示氢原子或 G表示完成5-至6-元杂环基所必需的非金属原子，W表示能够与由G构成的杂环基结合的取代基，t表示0〜4的整数，Het -1和Het-2独立地表示选自特定芳族杂环基团的基团。

公开(公告)号：US07581291B2

公开(公告)日：2009-09-01

申请号：US10548278

申请日：2004-03-05

申请人： Kenji Abe ,  Tomoaki Nakamura ,  Masahiko Yamanami

发明人： Kenji Abe ,  Tomoaki Nakamura ,  Masahiko Yamanami

IPC分类号： E05D3/10

CPC分类号： H04M1/0227 ,  E05D3/022 ,  E05D7/06 ,  E05Y2900/606 ,  G06F1/162 ,  G06F1/1679 ,  G06F1/1681 ,  Y10T16/525 ,  Y10T16/53864 ,  Y10T16/547 ,  Y10T16/5472 ,  Y10T16/5478

摘要： A compact hinge device is provided with which it is possible to turn two members and it is possible to make one of the members incline with respect to the other member. By a turning shaft part turning in a through hole in a first base member, a second base member constructed to turn together with the turning shaft part can be turned, and by an abutting part provided on the second base member sliding on a cam surface provided on the first base member the second base member can be made to incline with respect to the turning shaft part.

摘要翻译： 提供了一种紧凑的铰链装置，可以使两个构件转动，并且可以使其中一个构件相对于另一个构件倾斜。 通过转动第一基座部件中的通孔的转动轴部件，能够转动构造成与转动轴部一起转动的第二基体部件，并且通过设置在第二基部部件上的抵接部件在设置有凸轮面的部件上滑动 在第一基座构件上，第二基座构件可以相对于转动轴部分倾斜。