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    Active address table
    1.
    发明申请
    Active address table 审中-公开
    活动地址表

    公开(公告)号：US20070078879A1

    公开(公告)日：2007-04-05

    申请号：US11240977

    申请日：2005-09-30

    申请人： Robert Safranek ,  Aimee Wood ,  Herbert Hum ,  Robert Beers

    发明人： Robert Safranek ,  Aimee Wood ,  Herbert Hum ,  Robert Beers

    IPC分类号： G06F7/00

    CPC分类号： G06F12/0831 ,  G06F12/0813

    摘要： A structure referred to as an Active Address Table (AAT) may be used for cache coherence conflict resolution. The AAT may function to detect conflicting coherent requests to the same address and may ensure that each requesting entity receives a copy of the requested cache line in a cache line state-maintaining manner.

    摘要翻译： 称为活动地址表（AAT）的结构可用于高速缓存一致冲突解决。 AAT可以用于检测对相同地址的冲突相干请求，并且可以确保每个请求实体以高速缓存行状态维护方式接收所请求的高速缓存行的副本。

    Requester-generated forward the late conflicts in a cache coherency protocol
    2.
    发明申请
    Requester-generated forward the late conflicts in a cache coherency protocol 失效
    请求者产生转发高速缓存一致性协议中的后期冲突

    公开(公告)号：US20080005482A1

    公开(公告)日：2008-01-03

    申请号：US11479179

    申请日：2006-06-30

    申请人： Robert Beers ,  Herbert Hum

    发明人： Robert Beers ,  Herbert Hum

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F12/0828

    摘要： A method for resolving data request conflicts in a cache coherency protocol for multiple caching agents using requester-generated data forwards. In one embodiment, a caching agent stores information used to auto-generate a forward of data received in response to a data request.

    摘要翻译： 一种用于使用请求者生成的数据转发来解决多个缓存代理的高速缓存一致性协议中的数据请求冲突的方法。 在一个实施例中，高速缓存代理存储用于自动生成响应于数据请求而接收的数据的前向的信息。

    Non-speculative distributed conflict resolution for a cache coherency protocol
    3.
    发明申请
    Non-speculative distributed conflict resolution for a cache coherency protocol 有权

    公开(公告)号：US20050237941A1

    公开(公告)日：2005-10-27

    申请号：US11165688

    申请日：2005-06-24

    申请人： Robert Beers ,  Herbert Hum ,  James Goodman

    发明人： Robert Beers ,  Herbert Hum ,  James Goodman

    IPC分类号： G06F12/08 ,  H04L1/00

    CPC分类号： G06F12/0831 ,  G06F12/0813

    摘要： A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors all requests after that node has made its own request. If a line is in the Exclusive, Modified or Forward state, conflicts are resolved at the node holding the unique copy. The winner of the conflict resolution, and possibly the losers, report the conflict to the home node, which pairs conflict reports and issues forwarding instructions to assure that all requesting nodes eventually receive the requested data. If a requested cache line is either uncached or present only in the Shared state, the home node provides a copy of the cache node and resolves conflicts. In one embodiment, a blackout period after all responses until an acknowledgement message has been received allows all conflicting nodes to be aware of conflicts in which they are involved.

    Requester-generated forward for late conflicts in a cache coherency protocol
    4.
    发明授权
    Requester-generated forward for late conflicts in a cache coherency protocol 失效
    请求者生成转发缓存一致性协议中的后期冲突

    公开(公告)号：US07506108B2

    公开(公告)日：2009-03-17

    申请号：US11479179

    申请日：2006-06-30

    申请人： Robert Beers ,  Herbert Hum

    发明人： Robert Beers ,  Herbert Hum

    IPC分类号： G06F12/14 ,  G06F12/10

    CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F12/0828

    摘要： A method for resolving data request conflicts in a cache coherency protocol for multiple caching agents using requester-generated data forwards. In one embodiment, a caching agent stores information used to auto-generate a forward of data received in response to a data request.

    摘要翻译： 一种用于使用请求者生成的数据转发来解决多个缓存代理的高速缓存一致性协议中的数据请求冲突的方法。 在一个实施例中，高速缓存代理存储用于自动生成响应于数据请求而接收的数据的前向的信息。

    EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR
    5.
    发明申请
    EFFICIENT DATA TRANSFER BETWEEN A PROCESSOR CORE AND AN ACCELERATOR 有权
    加工商核心和加速器之间的有效数据传输

    公开(公告)号：US20150269074A1

    公开(公告)日：2015-09-24

    申请号：US14222792

    申请日：2014-03-24

    申请人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

    发明人： Pinkesh Shah ,  Herbert Hum ,  Lingdan Zeng

    IPC分类号： G06F12/08 ,  G06F13/28 ,  G06F12/12

    CPC分类号： G06F12/084 ,  G06F12/122 ,  G06F13/28 ,  G06F2212/601 ,  G06F2212/6042

    摘要： A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an accelerator that the input data is ready to be processed. The processor then determines that output data of the accelerator is ready to be consumed, the output data being located at the cache line or an additional cache line of the shared cache, wherein the cache line or the additional cache line comprises a set first flag that indicates the cache line or the additional cache line was modified by the accelerator and that prevents the output data from being removed from the cache line or the additional cache line until the output data is read by the processor. The processor reads and processes the output data from the cache line or the additional cache.

    摘要翻译： 处理器将输入数据写入共享高速缓存的高速缓存行，其中输入数据准备好由加速器操作。 然后通知加速器输入数据准备好进行处理。 处理器然后确定加速器的输出数据准备好被消耗，输出数据位于高速缓存行或共享高速缓存的附加高速缓存行，其中高速缓存线或附加高速缓存线包括设置的第一标志， 指示高速缓存行或附加高速缓存行被加速器修改，并且防止输出数据从高速缓存行或附加高速缓存行中移除，直到输出数据被处理器读取。 处理器从高速缓存行或附加高速缓存读取并处理输出数据。

    HYBRID INPUT/OUTPUT WRITE OPERATIONS
    6.
    发明申请
    HYBRID INPUT/OUTPUT WRITE OPERATIONS 审中-公开
    混合输入/输出写操作

    公开(公告)号：US20150113221A1

    公开(公告)日：2015-04-23

    申请号：US13997426

    申请日：2013-03-15

    申请人： Herbert Hum ,  Chandra Joshi ,  Rahul Pal ,  Luke Chang

    发明人： Herbert Hum ,  Chandra Joshi ,  Rahul Pal ,  Luke Chang

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0871 ,  G06F12/0875 ,  G06F2212/225 ,  G06F2212/452 ,  Y02D10/13

    摘要： A first processor receives a write request from an input/output (I/O) device connected to the first processor. The first processor determines whether the write request satisfies an allocating write criterion. Responsive to determining that the write request satisfies the allocating write criterion, the first processor writes data associated with the write request to a cache of the first processor.

    摘要翻译： 第一处理器从连接到第一处理器的输入/输出（I / O）设备接收写请求。 第一处理器确定写入请求是否满足分配写入标准。 响应于确定写请求满足分配写标准，第一处理器将与写请求相关联的数据写入第一处理器的高速缓存。

    Software constructed strands for execution on a multi-core architecture
    7.
    发明授权
    Software constructed strands for execution on a multi-core architecture 有权
    用于在多核架构上执行的软件构造的线

    公开(公告)号：US08789031B2

    公开(公告)日：2014-07-22

    申请号：US11901644

    申请日：2007-09-18

    申请人： Wei Liu ,  Lixin Su ,  Youfeng Wu ,  Herbert Hum

    发明人： Wei Liu ,  Lixin Su ,  Youfeng Wu ,  Herbert Hum

    IPC分类号： G06F9/45

    CPC分类号： G06F8/433

    摘要： In one embodiment, the present invention includes a software-controlled method of forming instruction strands. The software may include instructions to obtain code of a superblock including a plurality of basic blocks, build a dependency directed acyclic graph (DAG) for the code, sort nodes coupled by edges of the dependency DAG into a topological order, form strands from the nodes based on hardware constraints, rule constraints, and scheduling constraints, and generate executable code for the strands and store the executable code in a storage. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种形成指令串的软件控制方法。 软件可以包括用于获得包括多个基本块的超级块的代码的指令，为代码构建依赖性有向非循环图（DAG），将依赖性DAG的边缘耦合的分类节点排列成拓扑顺序，从节点形成线 基于硬件约束，规则约束和调度约束，并且生成链的可执行代码并将可执行代码存储在存储器中。 描述和要求保护其他实施例。

    SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX
    10.
    发明申请
    SYSTEM AND METHOD FOR RESERVATION STATION LOAD DEPENDENCY MATRIX 有权
    用于预留站负载依赖矩阵的系统和方法

    公开(公告)号：US20090328057A1

    公开(公告)日：2009-12-31

    申请号：US12164666

    申请日：2008-06-30

    申请人： Sagi LAHAV ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    发明人： Sagi LAHAV ,  Guy Patkin ,  Zeev Sperber ,  Herbert Hum ,  Shih-Lien Lu ,  Srikanth T. Srinivasan

    IPC分类号： G06F9/445

    CPC分类号： G06F9/3838 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3859

    摘要： A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding to each source value from which the first instruction depends. An indication may be made for each of the set of sources of the instruction, whether the source depends on a previously loaded value or source, where indicating may include storing a value corresponding to the indication. The instruction may be executed after the stored values associated with the instruction indicate the dependencies are satisfied.

    摘要翻译： 设备和方法可以获取用于执行的指令或微操作。 可以指示该指令是否取决于对应于一组先前获取的指令的任何源值。 可以存储对应于第一指令所依赖的每个源值的值。 可以针对指令的每个源的指示，源是否依赖于先前加载的值或源，其中指示可以包括存储对应于指示的值。 可以在与指令相关联的存储值表示满足依赖性之后执行指令。